04 January 2023, 04:58 | #1 |
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A4091 code converted to VHDL for A4092
I've been using an AI chat bot to translate PalAsm code into VHDL. WITH CODE COMMENTS!
Because of all the AI crashes it takes a long time... I think each bit of PalAsm code is for a different Macrocell in the PAL chips. Perhaps someone can confirm or correct? Once each macrocell has been converted to VHDL, then upgrading the A4091 to the A4092 can proceed The A4092 could be upgraded to the faster 53C720 chip. Allowing upgrading Remake A3000 motherboards to the faster 53C720 chip I was able to manually stitch this together with the bot's help. Code:
library ieee; use ieee.std_logic_1164.all; -- U303 is a device that manages arbitration of the A3090 and Zorro III buses. entity U303 is port ( C7M: in std_logic; -- Zorro III arbiter clock. MASTER: in std_logic; -- SCSI owns the A3090 bus. SBR: in std_logic; -- SCSI bus request. EBG: in std_logic; -- Expansion bus grant. FCS: in std_logic; -- Zorro III cycle strobe. SLAVE: in std_logic; -- Zorro III slave response. DTACK: in std_logic; -- Zorro III bus termination. BERR: in std_logic; -- Zorro III bus error. RST: in std_logic; -- Zorro III reset. CLK: in std_logic; -- NCR 53C710 bus clock. SMASTER: out std_logic; -- synched master for fall edge BLOCKBG: out std_logic; -- after 1st sbg block till end DMASTER: out std_logic; -- MASTER DELAYED. MYBUS: out std_logic; -- A3090 owns the Zorro III bus. SBG: out std_logic; -- SCSI bus grant. SSBR: out std_logic; -- SYNCHED SCSI bus req. REGED: out std_logic; -- A3090 is registered as a Zorro III master. EBR: out std_logic; -- Zorro III bus request. BMASTER: out std_logic -- Buffered/inverted version of MASTER. ); end entity; architecture Behavioral of U303 is -- signals for intermediate values signal SMASTER_int, BLOCKBG_int, DMASTER_int, MYBUS_int, SBG_int, SSBR_int, REGED_int, EBR_int, BMASTER_int, RCHNG_int : std_logic; begin -- The SCSI chip can be given the A3090 bus as soon as there's no activity on it. -- Hold onto it until the SCSI becomes master. SBG <= not FCS and not DTACK and not RST and SBR and EBG and not BLOCKBG_int and not (SMASTER_int and SBR) -- The SCSI chip can be given the A3090 bus as soon as there's no activity on it. Hold onto it until the SCSI becomes master. SSBR <= SBR and not RST -- synched scsi bus request BLOCKBG <= SBG -- after 1st sbg block till end MYBUS <= not SLAVE -- A3090 owns the Zorro III bus. SMASTER_int <= not CLK -- synched master for fall edge DMASTER_int <= not FCS and MYBUS and not SBG -- MASTER DELAYED. REGED <= not FCS and not DTACK and not RST and not BERR and SLAVE and MYBUS -- A3090 is registered as a Zorro III master. EBR <= not FCS and not DTACK and not RST and MYBUS and not SBG -- Zorro III bus request. -- synchronize signals with clock SMASTER <= SMASTER_int and not RST; -- synched master for fall edge DMASTER <= DMASTER_int and not RST; -- MASTER DELAYED. MYBUS <= MYBUS and not RST; -- A3090 owns the Zorro III bus. SBG <= SBG and not RST; -- SCSI bus grant. SSBR <= SSBR and not RST; -- synched scsi bus request REGED <= REGED and not RST; -- A3090 is registered as a Zorro III master. EBR <= EBR and not RST; -- Zorro III bus request. BMASTER <= not MASTER -- Buffered/inverted version of MASTER. RCHNG <= not FCS and not DTACK and not RST and not BERR and not SLAVE and MYBUS -- Registration is changing. end architecture; |
04 January 2023, 08:52 | #2 |
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The comments above certainly don't match the VHDL. Maybe they didn't match the original CUPL either?
There is an ancient tool to convert CUPL to other HDL languages such as VHDL/Verilog. Google long enough and you'll find it. I converted several CUPL, PALASM and ABEL projects to HDL in the past. I would : 1) Convert the Schematics into HDL first. This is a function of most schematic editors. 2) Merge the entities for all the GAL/PALs into one to get an overall I/O for all GAL/PALs. 3) Convert each GAL/PAL from CUPL to HDL and combine them into a single entity/module. 4) Mop-up any of the 74 series discrete logic parts which can also be integrated into the CPLD/FPGA. Last edited by alexh; 04 January 2023 at 11:30. |
05 January 2023, 02:54 | #3 | |||||
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Wow. This will be amazing as a coding teacher!
Here is a précis of the conversation with the AI helping me understand VHDL It taught useful points about VHDL: Quote:
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Quote:
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05 January 2023, 09:36 | #4 |
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I don't know anything about VHDL, but please take a chatbot's musings about any difficult subject with a huge grain of salt. Run the answers by someone who actually knows.
The chatbots can mansplain their way through anything with full confidence, even if the details are incorrect. |
05 January 2023, 09:40 | #5 | ||
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Quote:
e.g. Quote:
Last edited by alexh; 05 January 2023 at 17:00. |
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05 January 2023, 16:04 | #6 |
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Understand the target of these bots.
They aren't trained to give *correct* answers, they give answers that *read plausible*. |
06 January 2023, 12:39 | #7 | |
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Quote:
What of the actual VHDL example provided? Reading through this code is blowing on some very old dim embers to slowly heat up... maybe eventually Alexh, I think you might be the closest thing we have to an expert. How does it feel to be a volunteer |
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06 January 2023, 14:32 | #8 | |
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The VHDL is incorrect and does not match the original CUPL.
It hasn't really understood the CUPL language at all. Perhaps because you asked it to convert PALASM but the original files are actually written in CUPL? Quote:
I am not an expert on CUPL. I would have to re-learn the syntax to work out how it infers memory/registers. Last edited by alexh; 06 January 2023 at 14:49. |
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10 January 2023, 03:16 | #9 |
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One observation is that until movement is possible on Dave Haynie's reworked Buster project, the Buster-11 is still going to be your bottleneck. The 53C710, with Fast and Sync engaged, along with a suitable SCSI device, can push close to the theoretical ~10MB/sec if the bus it's on will go faster.
Even the most modern Z3 memory expansion can't push more than about 7-8MB/sec across it. |
12 January 2023, 09:09 | #10 | |
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Quote:
Zorro3 can become faster, supposedly similar to PCI speeds Perhaps a "BigRAM" bus could be added so it can connect to a Commodore A2630, or similar new card into an A2000 which lacks even a Zorro3 interface. New motherboards can also upgrade to this chip. Imagine an A3000 or A4000 with onboard 53c720. Perhaps similar to the A4000T which uses the 53c710. The CyberStorm uses the next chip up, the 53c770 (there's nothing in between despite the big number jump). That chip is a further advance on the 53c720. Additional to that, there are a bunch of OpenSource projects out there with code to be utilised for bridging purposes. Connecting IDE, ATAPI, and even SATA (legacy mode) can be achieved with 74fct163245 voltage levelers and some kind of SERDES deserialisation to convert SATA back to ATAPI. ATAPI uses a very similar chipset to SCSI. They are electrically incompatible, but that's easily fixed with 74xx244 or 74xx245 chips. Xilinx XC95288XL seems like a suitable CPLD to do the job. Its 5volt tolerant. But maybe jumping up to an FPGA might be a better idea. With the voltagle leveling chips, a 3.3Volt FPGA will be happily talking to the 5 volt SCSI bus fast enough to match an old SCSI HOST chip that can only manage 20MB/s |
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14 January 2023, 17:26 | #11 |
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It would be nice, yes, but be aware of the variables that would be faced.
Until your bus master card can drive the Zorro III expansion bus with burst transfers - and your target (ZIII card, Ramsey, or Accelerator card memory) also supporting that same burst protocol, you will have to fall back on the lowest common denominator of all three. There are very few A3K accelerator cards that can take advantage of an A3K with Ramsey memory using Static Column access, and therefore an improved burst access. Most configurations disable it because of the older Ramsey-04 and it's bugs having to be paired with the older SDMAC-02 (an SDMAC-04 and Ramsey-07 pairing is rare). A4000's Ramsey-07 use common DRAM on SIMMS, so no Static Column memory option there. Sync/Async interfacing reliability on the rest of the A3000/A4000 accelerators (with RAM) will be the next hurdle - Those that are stable with SDMAC DMA or the A4000T's 53C710 DMA will have the best chances. I've been watching the BFG9060 development thread. There is evidence of different levels of timing/tolerance in Buster/Super Gary/SDMAC/Ramsey interaction (and w/various expansion cards present) that they are diligently chasing down/trying to address. I hope to one day have one of these cards in hand (parts kit is in the hands of my builder), but I am on the sidelines for now, and I see & comprehend the variables they are facing between similar systems. Keep in mind that none of the expansion card developers, past or present, have had any kind of testing with the ZIII burst feature - so this will be new territory, and a good dose of YMMV is likely to apply. A note that any of the IDE-based interfacing you mention is still CPU-driven on the Amiga. On the Amiga, they are not bus-masters like SDMAC, or the 53C7xx family, although it can be made more efficient to be read with a burst-read or burst-write / multiple 32-bit longword CPU access. Most of off-shelf ATAPI-interface chips with DMA were focused on the PC market/mobo chipsets, and are generally incompatible with the Motorola 680x0 bus. Adding buffers and voltage levelers add additional logic delays, and you must still adhere to the limits of 5v logic propagation delays - again, the lowest common denominator scenario, and it also adds cost. Doing them from the ground up in custom logic parts is a huge amount of work, although may be a little cheaper. The 53c7xx family, though, was designed as a generic bus master with a SCSI logic engine behind it, and particularly targeted for 3.3/5v early PCI-based bus use, hence the use now and back then in the Amiga. It was widely compatible to 68030-era busses, and the Intel Pentium I/II, at the time. I remember them on the Novell and Windows servers that I worked on in the later 1990's. The BigRAM on the A2630 sits on the wrong side of the various busses. You would need a combo RAM and 53C7xx card for the back side of the A2630, and then note the slower 25MHz CPU bus of the 68030 being well off that of the 68040/68060 (even with the 68030 doing burst to this new memory space). A couple of mid-1990's 68040/060 accelerator 1-card designs took advantage of the faster CPU busses and the features of this SCSI/bus master chip. Last edited by thebajaguy; 14 January 2023 at 18:10. |
16 January 2023, 04:06 | #12 | |||
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Nice considered points thebajaguy
Quote:
Quote:
All the more reason to do it open source... Quote:
250ps voltage levelling chips can be used if necessary. ZuluSCSI is full of most of the needed code already in open source form. The 53c7xx family are all CPU local bus chips. Perhaps your thinking of the 53cx8xx family, which only supports PCI and lacks a local bus interface IIRC The 53c720 supports a choice of four bus modes : 68030, 68040, 386 and 486. Zorro3 would be 68030 mode with a CPLD doing the required fiddling of the signals. Perhaps using the "GottaGoFaZt3r Fast RAM" code and adapting it to translated SCSI bus PalASM code lifted from the 4091 might be a better way to go. I've only just begun to look at this modern card. BigRAM I believe has a bare 68030 bus. So its mostly just a physical challenge to make it work. If you need to switch sides, just a tiny plug in module with a ribbon cable to the other card or and SLI like PCB if the signals are not sufficiently clean. |
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16 January 2023, 09:20 | #13 |
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16 January 2023, 16:05 | #14 |
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@PurpleMelbourne - I just ordered a ZuluSCSI. I wanted to see what it can do, and I could use another SCSI target device on my bench.
On the A2630, and even the GVP Combo / G-Force cards (all have slightly different pinouts - sigh) the majority of the 68030 (or 68040 in the latter case) signals are all there - unbuffered. GVP only ever built the EGS 110/24 for theirs. C= only ever built their BigRAM example which has a corresponding product at iComp. I think I remember hearing that the A2630 back header may be missing some lines from the Amiga that would have made the rear connector more useful - the schematics are online, somewhere, IIRC. |
27 February 2024, 07:06 | #15 |
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How's this project going, @purplemelbourne? Did you have any success?
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27 February 2024, 09:59 | #16 |
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I don't think it went anywhere? CUPL is a very obscure language today. It is not surprising that ChatGPT (or whatever) has not been able to learn it simply by scraping the web. There are very few references and even fewer examples.
These links here should be enough for a human (who already knows VHDL/Verilog) to convert a CUPL program into a HDL like VHDL/Verilog for Synthesis. https://ece-classes.usc.edu/ee459/li..._Reference.pdf https://ww1.microchip.com/downloads/...oc/doc0737.pdf https://www.microchip.com/en-us/prod...sign-resources https://ww1.microchip.com/downloads/...es/doc3303.pdf https://mansfield-devine.com/specula...upl-and-cplds/ There are several examples of programs that do : VHDL/Verilog (Netlist) -> CUPL that could be used to check a conversion. https://www.edwinxp.com/VHDL-Editor-Build.aspx https://github.com/michaelhunsberger/JsonToCupl https://github.com/hoglet67/atf15xx_yosys https://whitequark.github.io/prjbureau/intro.html Last edited by alexh; 27 February 2024 at 10:07. |
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