06 November 2018, 17:48 | #21 | |
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Perhaps it's time for me to invest some more, err, time into understanding the CIA's Last edited by roondar; 06 November 2018 at 17:56. |
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06 November 2018, 18:10 | #22 |
Defendit numerus
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06 November 2018, 19:07 | #23 |
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Bogus interrupt should be fixed now. (Confirmed not happening in real A500)
CIA IRQ line is slightly delayed, it is possible to read set interrupt bit in ICR before chip's IRQ line gets activated. UAE internally puts interrupt trigger in a timer queue but it didn't check if it was already cleared (by CPU read of ICR) when timer expired. In this case real CIA still pulses IRQ line but as a side-effect it made emulation think CIA interrupt bit was still active and kept generating interrupt until ICR was read again (instead of generating single interrupt only). |
06 November 2018, 19:22 | #24 | |
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Thanks! |
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10 November 2018, 13:48 | #25 | |
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31 January 2019, 16:34 | #26 | |
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How the prgs work: The system is turned off, VBR is moved to FAST memory, all caches are turned on and only the VBI is enabled. A COPINT-interrupt is generated with a copperlist at rasterline $120. This interrupt is queried in a loop manually. In this loop a framecounter is increased from 1 until 3000 (1 Minute=50 FPS*60 s) for every COPINT acknowledge. After a COPINT acknowledge, the framecountercolour is written to the background colour register COLOR00 to show, that the test is in progress. If the framecounter reached 3000, the prg stops. Parallelly the generated VBI triggers a level-3-interrupt routine which also increases its own VBI-counter. Executed for the first time, it also triggers the framecounter once to start the counting. So both counters start with the same value within the same frame. At the end, both countervalues are printed in the Shell window to show if the VBI routine missed any acknowledge. Both prgs were tested on different A4000-060 machines and the test result was always the same (see enclosed screenshot). No difference between the 2xINTREQ version: Code:
move.w d0,INTREQ(a6) move.w d0,INTREQ(a6) movem.l (a7)+,d0-d7/a0-a6 rte Code:
move.w d0,INTREQ(a6) movem.l (a7)+,d0-d7/a0-a6 nop rte To my mind the nop version is sufficient and there is no 2x "move.w d0,INTREQ(a6)" needed on the A4000-060. Feel free to do your own tests on your A4000 and give me a feedback, please. |
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01 February 2019, 10:33 | #27 |
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I never had an 060 (well, that's not entirely true, I have a couple, but never had a cpu card for them), but I seem to remember that back in the day people were of the impression that is issue was worse on 040/A3640 than 060 systems?
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01 February 2019, 16:54 | #28 |
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Use of NOP is still technically wrong. Some fast RAM 68060 board can still fail (or some future board with overclocked CPU and/or very fast on board RAM, like ACA1260)
NOP only guarantees write has finished from CPU point of view, it won't guarantee following RTE can't finish before Paula notices the IPL change (1 extra CCK). |
01 February 2019, 18:20 | #29 | |
move.l #$c0ff33,throat
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My test code should still be on one of my A4k's, I'll check once I'm at my "Amiga cave" again (it's about 30km from my main flat). What I do remember is that I tested level 3 and level 6 interrupts, each with a plain and simple replayer so it was very easy to spot any interrupt bugs. |
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01 February 2019, 18:28 | #30 |
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I'm also using the NOP approach in this form, but only when I have a movem with several registers preceding it, like in your example. I guess the movem takes long enough, so that no problem ever occurs.
Without the movem, or only one or two registers to restore, I prefer to write to INTREQ twice, to be on the safe side. |
01 February 2019, 19:14 | #31 | |
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Normally, if the store buffer on the 68060 is enabled, operand writes using this buffer, the operand execution pieline incurs no stalls. But in the "cache inhibited, precise mode" this buffer is bypassed and system bus cycles are generated directly for each pipeline operation. This means, that each write operation is stalled for a minimum of five cycles. This also leads to a delay writing the the INTREQ register and shows how important it is to use the nop command for a bus syncronisation. |
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01 February 2019, 19:29 | #32 | |
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01 February 2019, 19:31 | #33 | |
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27 February 2019, 11:02 | #34 | ||
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27 February 2019, 12:23 | #35 |
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Hi dissident, to be even more precise (a bit pedantic?) chipmem data accesses are uncached.
This is fundamental in vanilla A1200 where you can interleave code in cache with any DMA access (Blitter et al.), even when BLTPRI is set, at full speed. In A500 you need to disable BLTPRI to work the same technique (so a slower overall). There is a good explanation of chip cacheability in WHDLoad docs: http://www.whdload.de/docs/en/cache.html#chipmem And yes, all accesses to the internal bus must comply with these rules (CHIP RAM, CUSTOM CHIPS, also the bogo RAM in A500). As always a very good note of Kalms |
27 February 2019, 17:49 | #36 | |||
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If the MMU is turned on by the system, the MMU tables define chip memory as "cache inhibited, imprecise" and transparent address translation is turned off. As instruction and data access use the same translation table tree and the user and supervisor rootpointers are initialized with the same root address, this definition counts for both. Chip memory won't be cached in any case. This may be one of the reasons why chip memory read accesses on a 68040/060 system are slower than on the 68020. As the vanilla A1200/020 has no data cache, there's nothing to worry about. Thanks for sharing the link of the chip cacheability in the WHDLoad docs. But there are some mistakes in it: Quote:
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27 February 2019, 19:31 | #37 | |||
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Yes, maybe my phrase in not written well, I meant to express this concept
If I don't remember wrong, some accelerators (wrongly) enable data cache for chip ram, causing various problems. Quote:
Never take anything for granted and complete your thoughts When you write in rush.. Quote:
In my "disable all" code I zero ESS in PCR register. Quote:
Later I'll take a look. |
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27 February 2019, 20:20 | #38 |
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