![]() |
Quote:
Any "normal" shifter bit combination does not seem to work fully correctly. I guess this needs logic analyzer check.. |
Quote:
This cractro only works if 3 bits gets injected (which fits with ACCC sequence) If B skip gets disabled: A goes to B. If Y skip gets disabled: X goes to Y and OUT This combination results in 3 bits without breaking my other test statefiles, including two lives crew lotus 2 cractro. EDIT: thanks to ross for logic analyzer trigger test executable :) |
Quote:
the cractro change AD -> ABCD. This happens in 2 situations: when Stage A or Stage X is active. first i thought it becomes CCCC with 3 shifter bits, but ACCC has 2 shifter bits. I built it in such a way that a 2nd shifter bit is added in both situations. |
Quote:
(there is actually only one situation, the (re)write with active blitter of different number of channels, in two possible different internal blitter shifter conditions). The difference at the 'change start' is this: - A BLTCON0 DACC-ACCC - D BLTCON0 ADAC-CCAC I can double check but I've only ever seen ACCC. But there is a difference when counter expires (i.e. last full cycle): - CCCACCCD-D - ACCCABCD-D Interesting, right? Don't ask me for more details because other in-depth tests need to be done :) But the fix made by Toni works perfectly for the current case and previous similar cases. |
Quote:
Quote:
seems like the blitter is trying to get back into its default behavior at the end. i get ACCC-D or ACC-D don't do any special here, cractro works anyway. something for todo list |
All times are GMT +2. The time now is 23:33. |
Powered by vBulletin® Version 3.8.11
Copyright ©2000 - 2024, vBulletin Solutions Inc.