Generic 16Mhz 68000 Accelerator Board

[Kai]

Dug this out of the internet (took a few days). It's originally designed for an Atari ST, although, i can't see why it'd be much different for the Amiga, or even a 68k based Macintosh.

Here's the schematic:



Here's the parts list:

Semiconductors:

IC1:     MC68000-16
         CPU 16MHz
IC2,IC3: IDT7174S-35 or CY7C185-15PC (15ns CMOS Parts)
         CACHE RAM 8K x 8bit 35ns
IC4,IC5: 6264-LP10 or CY7C185-20PXC (20ns CMOS Parts)
         CMOS-RAM 8K x 8bit 100ns
IC6:     GAL20V8-25
IC7,IC8: GAL16V8-25
IC9:     74AS00 4-NAND

Resistors:

R1-R4:   4.7 KOhm
R5:      200 Ohm

Capacitors:

C1-C9:   100nF Ceramic

Misc:

64-pin DIP Socket
2 x 32pin SIP Headers

Here's the GAL Equations:

IC6

Cache controller for MC68000
Address Decoding

*IDENTIFICATION
  CCDT1V1C;

*TYPE
  GAL20V8;

*PINS
  A23      = 1,
  A22      = 2,
  A21      = 3,
  A20      = 4,
  A19      = 5,
  A18      = 6,
  A17      = 7,
  A15      = 8,
  A13      = 9,
  A11      = 10,
  A9       = 11,
  A7       = 13,
  A8       = 14,
  A12.T       = 16,
  A14.T       = 17,
  A16.T       = 18,
  A6.T       = 19,
  MEM.T       = 20,        % RAM/ROM-Access %
  A10.T       = 21,
 /FCS.T       = 22,        % FPU Chip Select %
  A5       = 23;
  

*BOOLEAN-EQUATIONS

  A6.E = GND ;
  A10.E = GND ;
  A12.E = GND ;
  A14.E = GND ;
  A16.E = GND ;
  
  MEM = /A23 & /A22
      + A23 & A22 & A21 & A20 & A19 & A18 & /A16
      + A23 & A22 & A21 & A20 & A19 & A18 & /A17;
      
  FCS =  A23 & A22 & A21 & A20 & A19 & A18 & A16
       & A15 & A14 & A13 & A12 & A11 & /A10 & A9 & /A8 & /A7 & A6 & /A5;

*END

IC7

Cache controller for MC68000
Cache & Bus Control

*identification
CCDT2V6;

*type
GAL16V8;

*pins

/PAS    = 1,            % Delayed AS-Signal         %
/UDS    = 2,            % Upper Data Strobe (Processor) %
/LDS    = 3,            % Lower Data Strobe (Processor) %
/WR     = 4,            % Read/Write                    %
/AS     = 5,            % Address strobe (Processor)    %
 CEN    = 6,            % Cache On-Off                    %
 MEM    = 7,            % RAM/ROM-Zugriff               %
/BGACK  = 8,            % Bus Grant ACKnowledge            %
 HIT    = 9,            % Cache-Result                 %
 EN_I   = 11,            % Cache Enable (Feedback)   %
 ENAB.T = 12;           % Cache Enable (Output)        %
/CWE.T  = 13;            % Write Enable Cache-RAMs        %
/LDWE.T = 14;            % Write Enable lower Data RAM%
/UDWE.T = 15;            % Write Enable upper Data RAM %
/BLDS.T = 16,            % Lower Data Strobe (bus)       %
/BUDS.T = 17,            % Upper Data Strobe (bus)       %
/BAS.T  = 18,            % Address Strobe (bus)            %
/DOE.T    = 19,            % Output Enable Data-RAMs        %

*boolean-equations

 BAS.E = /BGACK;
 
 BAS = AS & PAS & /EN_I
      + AS & PAS & /MEM
      + AS & PAS & WR
      + AS & PAS & /HIT
      + AS & BAS;
      
 BLDS.E = /BGACK;
  
 BLDS = PAS & LDS & /EN_I
       + PAS & LDS & /MEM
       + PAS & LDS & WR
       + PAS & LDS & MEM & /WR & /HIT
       + PAS & UDS & MEM & /WR & /HIT
       + LDS & BLDS
       + UDS & BLDS;
       
 BUDS.E = /BGACK;
 
 BUDS = PAS & UDS & /EN_I
       + PAS & UDS & /MEM
       + PAS & UDS & WR
       + PAS & UDS & MEM & /WR & /HIT
       + PAS & LDS & MEM & /WR & /HIT
       + UDS & BUDS
       + LDS & BUDS;
       
 CWE = EN_I & BAS & ( UDS + LDS ) & MEM & /WR & /HIT
     + ( UDS + LDS ) & CWE;
     
 DOE = ( UDS + LDS ) & MEM & /WR & HIT & /CWE & EN_I;
 
 UDWE = EN_I & PAS & ( UDS + LDS ) & MEM & ( /WR & /HIT + WR & UDS & HIT )
      + ( UDS + LDS ) & UDWE ;

 LDWE = EN_I & PAS & ( UDS + LDS ) & MEM & ( /WR & /HIT + WR & LDS & HIT )
      + ( UDS + LDS ) & LDWE ;
      
 ENAB = /AS & CEN + AS & EN_I + CEN & EN_I ;
      

*END

IC8

Cache controller for MC68000
DTACK control & Cache Refresh

*identification
CCDT3V8;

*type
GAL16V8;

*pins

 CL8    = 2,            % 8 Mhz Clock                    %
/SDT    = 3,            % System DTack                  %
/FCS    = 4,            % FPU Chip Select               %
/RESET  = 5,            % Reset                         %
/BGACK  = 6,            % Bus Grant ACKnowledge            %
 MEM    = 7,            % RAM/ROM-Access             %
/WR     = 8,            % Read/Write                    %
 HIT    = 9,            % Cache-Result                 %
 ST0.R  = 12,           % Bit 0 State Encoding   %
/PDT.T  = 13,           % Processor DTACK                %
 ST1.R  = 14,           % Bit 1 State Encoding   %
 ST2.R  = 15,           % Bit 2 State Encoding   %
/PAS.R  = 16,           % Delayed AS-Signal         %
/CLR.T  = 17,            % Cache-Refresh                %
/AS.T   = 18,           % Address strobe (Input)      %
 ENAB.T = 19;           % Cache Enable (Input)        %

*boolean-equations

 ENAB.E = GND ;
  
 AS.E = GND ;
 
 CLR = BGACK + RESET + /ENAB ;
 
 PDT = ST2 & /ST1 & /ST0 & PAS        % Condition S5 %
      + ST2 & /ST1 &  ST0 & PAS        % Condition S6 %
      + ST2 &  ST1 &  ST0 & PAS        % Condition S8 %
      + FCS & AS & SDT;                % FPU-Access %
      
     ST0 = AS & /RESET & /FCS & /PAS
          + AS & /RESET & ST1 & /ST0
          + AS & /SDT & /RESET & /ST2 & ST1
          + AS & /CL8 & /RESET & /ST2 & ST1
          + /RESET & ST2 & /ST0
          + AS & /WR & /RESET & ST2 & ST1;
          
     ST1 = AS & MEM & HIT & /WR & ENAB & /RESET & /FCS & /PAS
         + AS & /RESET & /FCS & /ST2 & /ST1 & ST0
         + AS & /RESET & ST1 & /ST0
         + AS & /SDT & /RESET & /ST2 & ST1
         + AS & /CL8 & /RESET & /ST2 & ST1
         + AS & /WR & /RESET & ST2 & ST1;
         
     ST2 = AS & MEM & HIT & /WR & ENAB & /RESET & /FCS & /PAS
         + AS & SDT & CL8 & /RESET & /ST2 & ST1 & ST0
         + /RESET & ST2 & /ST0
         + AS & /WR & /RESET & ST2 & ST1;
         
    /PAS = RESET
         + ST2 & /ST1 & ST0
         + WR & ST2 & ST1
         + /AS & ST0
         + /FCS & /ST2 & /ST1 & /ST0 & PAS
         + /AS & /ST2;

*END

So what do you guys reckon? Anyone feel like knocking up a PCB or a Gerber?

[Jope]

Look at Aminet, this was done for the Amiga too in a compatible fashion.

http://aminet.net/package/docs/hard/14MhzA500

Perhaps RedskullDC himself could elaborate whether it had the slowdown for disk access support in it, I'm too busy to check it out right now.

[Kai]

From the looks of the link you sent me, that 14Mhz one has no Cache...

[Jope]

Right you are. However I believe you would have to use ideas from the other to get the one you pasted to work in an Amiga.

[SpeedGeek]

If you modified this design to disable caching of chip memory and fixed the address decoding for Amiga's memory map you could use this on an Amiga. But why fool around with a 68000 when a 68020/68030 could support 32 bit fast memory, FPU, MMU and other features you expect from a decent accelerator card?

[pandy71]

E clock will be twice faster - CIA will not work correctly - E clock must be generated externally and with DTACK 0.7MHz cycle simulated (exactly as in Gayle)
Cache is great idea - can be used with 68020/68030 or similar CPU

[Kai]

68030 at least, i know is capable of addressing upto 256kb of L2 cache - as the pins exist to select it & be transparent to the system (when external cache is installed, its treated as internal cache, rather than system memory). Not sure about the 68020, and the 68000 had no internal caches, or external, hence the addition of 16kb of it on this design.

True - why bother with a 68000 when you could go for one of the others, but, the more information, schematics and stuff i can throw into the ring, the better - it's all adaptable

[Zetr0]

now, this is very interesting =)

[Kai]

Remember - the Macintosh IIci was a 68030 @ 25Mhz with a 68882 FPU and an optional 32k SRAM L2 Cache card. It connects directly to the A/D buses - the only thing i can figure out, is the cache controller - probably not much different than the PAL/GAL setup on this, and the PAK accelerators.

[SpeedGeek]

@pandy71
If the host Amiga has a motherboard 68000 present (i.e. A500,A2000) you don't need to worry about E clock. The 68000 continues to output the E clock even when another CPU masters the bus. Gayle and Fat Gary generate E clock on Amigas without a motherboard 68000.

@Zetr0
Since I don't own a small box Amiga, and I have way to many hack projects keeping me busy, I'd say the ball is in your court!

[pandy71]

Originally Posted by SpeedGeek

@pandy71
If the host Amiga has a motherboard 68000 present (i.e. A500,A2000) you don't need to worry about E clock. The 68000 continues to output the E clock even when another CPU masters the bus. Gayle and Fat Gary generate E clock on Amigas without a motherboard 68000.

Nope - E clock is 1/10 asynchronous clock generated in 68000 in a kind of ring counter - for 8MHz it is around 0.8MHz - CIA works correctly but for 16MHz it will be 1.6MHz, CIA will work twice fast or not work at all (but anyway all timing related to CIA will be wrong).
A600 not use E clock from CPU but from Gayle - for any accelerator for Amiga
without Gayle or similar function, E clock must be generated externally and all bus timing related to VPA IC's implemented by DTACK.

BTW
MC68000 accel board can be usefulldue of simplicity - 68020 need more complicated board - twice as in 68000 case number of DATA lines make PCB more complicated - 68000 PCB can be made in home with iron on 2 layers, 68020 probably need 4 layer PCB ie at start it is more serious project.

[Kai]

Pandy - the PAK68 i already posted was a 68020 board that plugs into the 68k socket. 2-layer PCB only.

[SpeedGeek]

@pandy71

If you replace the motherboard 7 Mhz 68000 with a 16 Mhz 68000 then you would have an E clock timing problem but if you leave the motherboard 7 Mhz 68000 present on the motherboard (A2000) or the Accelerator card has a socket for the original 68000 (A500) it can still generate the proper E clock! This also makes it possible to reboot in 7 Mhz 68000 mode.

[pandy71]

Originally Posted by Kai

Pandy - the PAK68 i already posted was a 68020 board that plugs into the 68k socket. 2-layer PCB only.

Doable but not recommended especially for higher speeds...

Originally Posted by SpeedGeek

@pandy71

If you replace the motherboard 7 Mhz 68000 with a 16 Mhz 68000 then you would have an E clock timing problem but if you leave the motherboard 7 Mhz 68000 present on the motherboard (A2000) or the Accelerator card has a socket for the original 68000 (A500) it can still generate the proper E clock! This also makes it possible to reboot in 7 Mhz 68000 mode.

Sorry but not, CPU system will not work that way - if You clock Your CPU with twice higher clock, E clock will be also twice faster, CIA as IC can work but ALL CIA timing will be twice faster - this is not acceptable from Amiga point of view - E clock must remains constant for all time - ie You must supply to CIA's 0.7MHz clock and for non 7.xxx MHz 68000 You must create E clock and care about all VMA/VPA/E bus cycles in a way that will be transparent from CIA's point of view (recreate MC68000 functionality) - this is not very big problem, usually is made in one GAL/PAL.

[SpeedGeek]

@pandy71
My A2000 w/A2630 already works that way! The 68030 masters the bus and the motherboard continues to get the E clock from the 7 Mhz 68000. Why is this so difficult to understand?

[Zetr0]

I think where Pandy71 is getting caught up is -

If the Host (7 mhz CPU) is held in RESET then the ECLK can not be generated by that CPU. As such will fail when handling VMA/VPA and E

Personally I am unsure if after BG/BA handshaking the HOST CPU in to RST and letting the other (14Mhz) carry on - will the HOST CPU would still burst ECLK while RST?.

Another concern is what about the Target CPU running at 14Mhz, what about the 7Mhz Bus, we will need to slow-down to negotiate that (DTACK)... the cache will help immensely here

Hmmmm.... looks like I may need to dust off the 'ol 68000 bible again =)

A very smart chap - Livio Plos actually produced a working 14Mhz version (without cache) and based on simple 74 logic.... it should also be simple to augment the design with 16KB of Cache.




@SpeedGeek

If you are interested I have an A500 Rev 1.3 motherboard here for fun and games if you want it.


@Pandy

A two layer board reasonably designed should see 28 / 33Mhz frequency operation.

[Kai]

Look a the design of the LUCAS accelerator - they still manage to provide the all important E clock at the right speed - despite having the 68020 and 68881 clocked at 16Mhz

[SpeedGeek]

@Zetr0
from my October, 1985 Motorola 68000 manual:
"E is a free-running clock and runs regardless of the state of the bus on the MPU."

The A2630 logic does not keep the motherboard 68000 in reset. In fact since reset is common to all the custom chips it's essentially a full motherboard reset! The A2630 simply asserts BR to the 68000 and waits for the 68000 BG. When BG is acknowledged the A2630 asserts BGACK and masters the bus until the next reset or some other Zorro2 device requests the bus.

Thanks for the A500 offer but I already have to many unfinished projects on my "To Do" list.

[pandy71]

Originally Posted by SpeedGeek

@pandy71
My A2000 w/A2630 already works that way! The 68030 masters the bus and the motherboard continues to get the E clock from the 7 Mhz 68000. Why is this so difficult to understand?

Please check A2620 PAL equations for U308 and U309.

Originally Posted by Kai

Look a the design of the LUCAS accelerator - they still manage to provide the all important E clock at the right speed - despite having the 68020 and 68881 clocked at 16Mhz

Please check PAL U4 equations.

Originally Posted by Zetr0

@Pandy

A two layer board reasonably designed should see 28 / 33Mhz frequency operation.

I saw plenty 2 layers PCB's that works even on 13GHz but usually as antennas and this is my point - accelerator without RAM (fast, 32 bit access) have no sense at all - imagine using for example some DDR/DDR2/DDR3 RAM chip even as a RAD-like device

Originally Posted by SpeedGeek

@Zetr0
from my October, 1985 Motorola 68000 manual:
"E is a free-running clock and runs regardless of the state of the bus on the MPU."

The A2630 logic does not keep the motherboard 68000 in reset. In fact since reset is common to all the custom chips it's essentially a full motherboard reset! The A2630 simply asserts BR to the 68000 and waits for the 68000 BG. When BG is acknowledged the A2630 asserts BGACK and masters the bus until the next reset or some other Zorro2 device requests the bus.

Why Commodore implement Gayle as E source? all CIA'a timing on A600 is performed by Gayle - from CPU point of view this is fully asynchronous design with DTACK.

[SpeedGeek]

Originally Posted by pandy71

Please check A2620 PAL equations for U308 and U309.

Why Commodore implement Gayle as E source? all CIA'a timing on A600 is performed by Gayle - from CPU point of view this is fully asynchronous design with DTACK.

WTF do A2620 PAL's have to do with A2630?
From A2630 U504 rev 3
"This sync-up is only required when the board is in a B2000, since that board will be receiving E from the motherboard."

A1200 has 68020 on motherboard and Gayle generates E clock. A3000 and A4000 have 68030 or 68040 and Fat Gary generates E clock. It's a "No Brainer" that 020,030 and 040 have no E clock output! On A600 it looks like the coin flip went to Gayle for E clock generation.