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Old 05 July 2008, 00:34   #1
rkauer
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Skilled people who wants to help in CPLD programming

Hello.

I want someone who can program a Xilinx FPGA. I have the logical schematics (hand-drawn) and point the needed output ports.

Can someone help coding it or point me where to learn to program/code it?
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Old 05 July 2008, 01:10   #2
alexh
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What do you mean program?? FPGA's are not (generally) static, meaning that when you remove the power they loose their program.

They are generally programmed on power up from a EPROM sometimes using assistance from a uController or a PLD.

[Edit] Oh I see you mean "Program" not "Program" why didnt you say

You want to learn a HDL programming language? Any preference? I am fluent in VHDL, system verilog and system C if you want any help.

You sure you want to be using an FPGA?? It's probably too big, you probably want to use a CPLD.
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Old 05 July 2008, 01:11   #3
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Post the schematic and as much detail as you can stand and I'll convert it into VHDL for you. (You'll have to include details about tristated signals.)

Or why not go old-skool and use a schematic capture tool (schematic -> netlist or schematic -> HDL) then you can do it all yourself.
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Old 05 July 2008, 01:21   #4
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Quote:
Originally Posted by alexh View Post
What do you mean program?? FPGA's are not (generally) static, meaning that when you remove the power they loose their program.
Ups! CPLD then. I always thinks the names are equivalents!

Quote:
They are generally programmed on power up from a EPROM sometimes using assistance from a uController or a PLD.

[Edit] Oh I see you mean "Program" not "Program" why didn't you say
Yeah, I meaning CPLD. But the language is the same, AFAIR. Only CPLD is static.

Quote:
You want to learn a HDL programming language? Any preference? I am fluent in VHDL, system verilog and system C if you want any help.
Thanks, verilog is good enough! Much thanks for it Alex!

I'm intending only to translate the logic circuit into CPLD code to "burn" the chip.

Quote:
You sure you want to be using an FPGA?? It's probably too big, you probably want to use a CPLD.
Thanks for the correction, that's the thing I want.

A humble 128 gates will be more than enough for the project. It will use 6 gates for hand-shaking between CPUs and up to 80 to create a mux-demux (memory address router). If I find a code for a SDRAM controller...
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Old 05 July 2008, 01:25   #5
rkauer
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BTW: anyone have the content of the QuickLogic's QL8x12A - OPL68C used in the Microbotics MBX1230XA?

A friend of mine fried the chip...

And he asked me(!) for a repair!

Any help will be welcome!
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