Generic 16Mhz 68000 Accelerator Board
Dug this out of the internet (took a few days). It's originally designed for an Atari ST, although, i can't see why it'd be much different for the Amiga, or even a 68k based Macintosh.
Here's the schematic: http://kai.robinson.free.fr/dropbox/...accelschem.gif Here's the parts list: Code:
Semiconductors: IC6 Code:
Cache controller for MC68000 Code:
Cache controller for MC68000 Code:
Cache controller for MC68000 |
Look at Aminet, this was done for the Amiga too in a compatible fashion.
http://aminet.net/package/docs/hard/14MhzA500 Perhaps RedskullDC himself could elaborate whether it had the slowdown for disk access support in it, I'm too busy to check it out right now. |
From the looks of the link you sent me, that 14Mhz one has no Cache...
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Right you are. However I believe you would have to use ideas from the other to get the one you pasted to work in an Amiga.
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If you modified this design to disable caching of chip memory and fixed the address decoding for Amiga's memory map you could use this on an Amiga. But why fool around with a 68000 when a 68020/68030 could support 32 bit fast memory, FPU, MMU and other features you expect from a decent accelerator card?
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E clock will be twice faster - CIA will not work correctly - E clock must be generated externally and with DTACK 0.7MHz cycle simulated (exactly as in Gayle)
Cache is great idea - can be used with 68020/68030 or similar CPU |
68030 at least, i know is capable of addressing upto 256kb of L2 cache - as the pins exist to select it & be transparent to the system (when external cache is installed, its treated as internal cache, rather than system memory). Not sure about the 68020, and the 68000 had no internal caches, or external, hence the addition of 16kb of it on this design.
True - why bother with a 68000 when you could go for one of the others, but, the more information, schematics and stuff i can throw into the ring, the better - it's all adaptable :) |
now, this is very interesting =)
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Remember - the Macintosh IIci was a 68030 @ 25Mhz with a 68882 FPU and an optional 32k SRAM L2 Cache card. It connects directly to the A/D buses - the only thing i can figure out, is the cache controller - probably not much different than the PAL/GAL setup on this, and the PAK accelerators.
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@pandy71
If the host Amiga has a motherboard 68000 present (i.e. A500,A2000) you don't need to worry about E clock. The 68000 continues to output the E clock even when another CPU masters the bus. Gayle and Fat Gary generate E clock on Amigas without a motherboard 68000. @Zetr0 Since I don't own a small box Amiga, and I have way to many hack projects keeping me busy, I'd say the ball is in your court! |
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A600 not use E clock from CPU but from Gayle - for any accelerator for Amiga without Gayle or similar function, E clock must be generated externally and all bus timing related to VPA IC's implemented by DTACK. BTW MC68000 accel board can be usefulldue of simplicity - 68020 need more complicated board - twice as in 68000 case number of DATA lines make PCB more complicated - 68000 PCB can be made in home with iron on 2 layers, 68020 probably need 4 layer PCB ie at start it is more serious project. |
Pandy - the PAK68 i already posted was a 68020 board that plugs into the 68k socket. 2-layer PCB only.
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@pandy71
If you replace the motherboard 7 Mhz 68000 with a 16 Mhz 68000 then you would have an E clock timing problem but if you leave the motherboard 7 Mhz 68000 present on the motherboard (A2000) or the Accelerator card has a socket for the original 68000 (A500) it can still generate the proper E clock! This also makes it possible to reboot in 7 Mhz 68000 mode. |
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@pandy71
My A2000 w/A2630 already works that way! The 68030 masters the bus and the motherboard continues to get the E clock from the 7 Mhz 68000. Why is this so difficult to understand? |
I think where Pandy71 is getting caught up is -
If the Host (7 mhz CPU) is held in RESET then the ECLK can not be generated by that CPU. As such will fail when handling VMA/VPA and E Personally I am unsure if after BG/BA handshaking the HOST CPU in to RST and letting the other (14Mhz) carry on - will the HOST CPU would still burst ECLK while RST?. Another concern is what about the Target CPU running at 14Mhz, what about the 7Mhz Bus, we will need to slow-down to negotiate that (DTACK)... the cache will help immensely here Hmmmm.... looks like I may need to dust off the 'ol 68000 bible again =) A very smart chap - Livio Plos actually produced a working 14Mhz version (without cache) and based on simple 74 logic.... it should also be simple to augment the design with 16KB of Cache. http://s3.postimage.org/ibwnfpxup/ACCEL.png @SpeedGeek If you are interested I have an A500 Rev 1.3 motherboard here for fun and games if you want it. @Pandy A two layer board reasonably designed should see 28 / 33Mhz frequency operation. |
Look a the design of the LUCAS accelerator - they still manage to provide the all important E clock at the right speed - despite having the 68020 and 68881 clocked at 16Mhz
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@Zetr0
from my October, 1985 Motorola 68000 manual: "E is a free-running clock and runs regardless of the state of the bus on the MPU." The A2630 logic does not keep the motherboard 68000 in reset. In fact since reset is common to all the custom chips it's essentially a full motherboard reset! The A2630 simply asserts BR to the 68000 and waits for the 68000 BG. When BG is acknowledged the A2630 asserts BGACK and masters the bus until the next reset or some other Zorro2 device requests the bus. Thanks for the A500 offer but I already have to many unfinished projects on my "To Do" list. |
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From A2630 U504 rev 3 "This sync-up is only required when the board is in a B2000, since that board will be receiving E from the motherboard." A1200 has 68020 on motherboard and Gayle generates E clock. A3000 and A4000 have 68030 or 68040 and Fat Gary generates E clock. It's a "No Brainer" that 020,030 and 040 have no E clock output! On A600 it looks like the coin flip went to Gayle for E clock generation. |
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