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#1 |
Registered User
Join Date: Feb 2011
Location: Italy/Rome
Posts: 2,344
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Horizontal Blanking
Hi All
I would like to trigger an interrupt every time that the Horizontal Blanking occur, How could I do that? It's a been long time since my last conding for Amiga, and I have to polish my skills a bit ![]() thanks a lot |
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#2 |
Join Date: Jul 2008
Location: Sweden
Posts: 2,269
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Trigger the interrupt with a write to INTREQ in your Copper program.
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#3 |
move.l #$c0ff33,throat
Join Date: Dec 2005
Location: Berlin/Joymoney
Posts: 6,863
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I suppose you mean the vertical blanking interval here? If so, patch the level 3 interrupt vector ($6c.w, take care of the VBR on 680x0 CPU's) and enable the the level 3 interrupt in INTENA (bit 5, VERTB).
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#4 |
Computer Nerd
Join Date: Sep 2007
Location: Rotterdam/Netherlands
Age: 48
Posts: 3,831
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And if not, then make a copper list that waits for the end (or start) of each scan line and trigger a copper interrupt after that.
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#5 |
Registered User
Join Date: Feb 2011
Location: Italy/Rome
Posts: 2,344
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Thanks for your helps. I meant Horizontal not Vertical Blanking. I would like to do some test
in order to take advantage of this Horizontal blanking, Like copy speed. So I have to write a copperlist that wait all the lines (200 or 256), and after each wait, I have to a move that trigger this Interrupt, doesn't ? thanks |
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#6 |
gone
Join Date: Apr 2007
Location: completely gone
Posts: 1,596
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You would have to wait for the first non visible horizontal wait pos on the right hand edge of each scanline and then trigger your interrupt by writing intreq.
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#7 |
WinUAE developer
Join Date: Aug 2001
Location: Hämeenlinna/Finland
Age: 49
Posts: 26,553
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What kind of setup? Use of "hblank" interrupts on non-fast RAM/<68020 CPU setup is waste of CPU time. It takes over 50 CPU cycles to enter and exit an interrupt.
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#8 |
move.l #$c0ff33,throat
Join Date: Dec 2005
Location: Berlin/Joymoney
Posts: 6,863
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I am still not sure that you mean horizontal blanking. (TC) C2P copyspeed routines (if that is what you're referring to with copyspeed) take advantage of the vertical blanking because chipmem access is faster then.
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#9 |
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Join Date: Feb 2011
Location: Italy/Rome
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StingRay,
Yes I meant horizontal blanking too. I would like to see what kind of outcome I'll see. Just to test... |
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#10 |
gone
Join Date: Apr 2007
Location: completely gone
Posts: 1,596
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Still don't get what you're trying to do personally - post your test code maybe?
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#11 |
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Join Date: Feb 2011
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Just to see how quick or how slow could be to works with chip-mem when bitplane DMA aren't using it. I still have to write my code..
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#12 |
move.l #$c0ff33,throat
Join Date: Dec 2005
Location: Berlin/Joymoney
Posts: 6,863
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#13 |
Registered User
Join Date: Feb 2011
Location: Italy/Rome
Posts: 2,344
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hehe! Nothing fancy. Just to play with interrupts.
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#14 |
Computer Nerd
Join Date: Sep 2007
Location: Rotterdam/Netherlands
Age: 48
Posts: 3,831
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sandruzzo just wants to know how much speed can be gained if you also use the horizontal blank and not just the vertical one.
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#15 |
move.l #$c0ff33,throat
Join Date: Dec 2005
Location: Berlin/Joymoney
Posts: 6,863
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I understood that. It still doesn't make sense to me!
Last edited by StingRay; 16 January 2012 at 19:42. Reason: typo |
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#16 |
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Join Date: Feb 2011
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Thorham
I don't know how much speed can be gained. I want to see what would be difference about accessing during Hblank or during normal rasterline. |
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#17 |
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Join Date: Nov 2006
Location: Stockholm, Sweden
Posts: 237
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You can do some estimations at least.
A line is approximately 228 buscycles. If you have a 320 pixels wide lores screen, then the bitplane DMA-on portion of that screen is 160 buscycles. So you have 160 buscycles worth of DMA-on and 68 buscycles of DMA-off. During the DMA-on portion, on a lores screen you will only see a performance degradation if you have more than 4 bitplanes active. On an A500, having 5 bitplanes active will steal 25% of the DMA slots. On an A1200, having 5/6/7/8 bitplanes active will steal 6.25%/12.5%/18.75%/25% of the DMA slots, respectively. (If you are running in hires/shres then a lot more buscycles will be used up by bitplane DMA.) Now the kicker is, how much time do you lose by triggering the interrupt? if you target another machine than standard a500, how do you adjust the amount of work being done during the interrupt to match the performance of the machine? I never tried it myself because I assumed that the overhead of the hblank interrupt would outweigh the few buscycles saved. Also, I normally target faster machines and there it is difficult to make the code self-adjusting. |
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#18 | |
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Join Date: Jan 2012
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Quote:
My advice would be to experiment with a copper list that triggers interrupts at various places along each horizontal line to discover when you get the greatest level of concurrency. The proper place will most likely vary with the instruction sequence you wish to execute. It's possible the best place to trigger an interrupt is somewhere in the middle of a scan line. Other programmers are forced to interrupt on hblank or vblack. You have an Amiga. You can trigger an interrupt whenever you damn well please. ![]() |
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#19 |
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Join Date: Feb 2011
Location: Italy/Rome
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Kalms , mc6809e
thanks for your reply. I just want to play a little bit with Amiga interrupt, like I neved did, and see if I can get a better blittler and cpu work when they have as much cycle as possible. but since you already did it... |
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