09 July 2024, 13:02 | #1 |
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mSATA to 44 pin IDE adapter?
Since the SD-card solution I ended up using on my A500 feels far from ideal and is quite slow I've started looking for alternatives.
Found this thing and wonder if this is a feasible way to go, paired with a decently sized mSATA SSD? https://www.amazon.se/h%C3%A5rddisk-...07VG1X6L3?th=1 |
09 July 2024, 13:21 | #2 | |
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I have a few of these. They are hit and miss. You have to get right SSD that will work with Amiga. I bought 3 16GB SSD's before I got one that worked. |
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09 July 2024, 15:57 | #3 |
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The speed will be limited by your IDE controller implementation and your CPU power. 68000 @ 7MHz with PIO0 you will be limited to approx 500/600 Kbytes/sec which is very slow but there is nothing you can do about it other than to buy a CPU accelerator or SCSI DMA controller
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10 July 2024, 00:11 | #4 | |
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The SD-card adapter I'm using now is very slow. According to Sysinfo a little under 700k/s but I really doubt that, it feels slower. I don't expect to get the speed I had with the GVP SCSI but at least a bit better than this. |
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10 July 2024, 09:49 | #5 | |
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That is slow, I would expect atleast 1.1 to 1.2mb/sec with acceleration. |
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10 July 2024, 12:00 | #6 | |
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Consider using diskspeed and not sysinfo to get your figures. |
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10 July 2024, 12:59 | #7 | |
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Well, this is odd. I ran Diskspeed before and after. According to the results Create file and Write to file actually got a lot slower while Read from file became a lot faster. Last edited by Liqourice; 10 July 2024 at 13:38. |
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10 July 2024, 15:13 | #8 |
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Interesting. How much slower and how much faster?
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10 July 2024, 17:11 | #9 |
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10 July 2024, 21:08 | #10 |
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How would this thing work considering there's no need for an adapter?
https://www.transcend-info.com/embed...lutions/psd330 |
11 July 2024, 00:30 | #11 |
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I still think you've got a setup issue. Might be worth telling us what file system you have installed and what buffers the drive has. Maybe post your startup sequence too?
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11 July 2024, 01:03 | #12 | |
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It's FFS Intl no directory cache 4k block size, 0xFE00 maxtransfer. 8GB SD-card but only using 4. SS is an old mess, been hanging around since 1992 and Kick 2.04. Thinking I'm gonna try a fresh install but waiting until I can get my hands on 3.2.2. Running 3.1 now. Might just leave it as it is for now until I can put 3.2 in. I guess there is some kind of misdirected pride in continuing to build on the same first install I had when I got my first harddrive. |
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11 July 2024, 11:02 | #13 |
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0xFE00 MaxTransfer is unnecessary limiting, 0x1FE00 is enough to avoid the bug in 3.1 scsi.device.
Also verify that your Mask isn’t set to something really strange. It should be default 0x7FFFFFFE, but can even be completely unlimited at 0xFFFFFFFF with the C= IDE scsi.device, it has no memory region or alignment access bugs as it copies all the data using the CPU. |
11 July 2024, 11:19 | #14 |
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11 July 2024, 11:34 | #15 | |
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HDToolBox works, at least if you did the initial partitioning with it. I often use Thomas Rapp’s excellent ChangeBootPri to view and change these: https://thomas-rapp.hier-im-netz.de/download.html |
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11 July 2024, 11:59 | #16 |
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I'd be curious to know if changing MaxTransfer affects the performance. I understand why it could but I'd like to know if it does in practice.
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11 July 2024, 12:12 | #17 | |
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However, it is unnecessary to set a limit at about half what is needed to avoid the bug, thats why I recommended to fix it. The Mask is "easier" to fudge the performance with - say the Mask is for unknown reason set to limit to Zorro2 address space of first 16MB - Mask = 0xFFFFFE or similar: Then when running with the TF536, which has all memory above first 16MB, the filesystem will think it is unsafe to do direct transfers to/from that memory, as instructed by the Mask and will instead copy the data to chipmem and transfer it in small blocks in an attempt to make the transfer safe: - chipmem as DMA controllers usually at least can access that - small blocks as that with many controllers actually makes them avoid using DMA and revert to PIO In this case that is a moot point as DMA does not exist as the C= IDE is a PIO controller, but the filesystem does not know and acts as instructed by the Mask and fudges the performance for no good reason. |
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11 July 2024, 12:26 | #18 |
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Was it so that when using C as last letter with the Mask, it will be 32bit aligned?
E.g., Mask 7FFFFFFC (Any memory - 32 bit aligned). |
11 July 2024, 12:30 | #19 | |
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11 July 2024, 12:41 | #20 | ||
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Also keep in mind that the Mask does not align anything, it is used to restrict direct transfers to/from memory to addresses not matching the mask. So "address AND Mask == address" must be true: What I want to say by this is that nothing will get faster by say using Mask 7FFFFFFC instead of say 7FFFFFFF, only slower as it makes the filesystem to the safe and very slow transfers if the address of transfer does not match the Mask. Only limit with the Mask if you need it to avoid a bug/limitation in the driver+hardware, else you will only end up with very slow transfers for no good reason. This speed difference is only seen if tested through filesystem access. SysInfo, SCSISpeed, RSCP etc does direct device access. You need say DiskSpeed (found on aminet), which also can test speed at different alignment - watch speed of WORD and BYTE transfers in DiskSpeed decrease enormously if you change Mask 7FFFFFFF -> 7FFFFFFC for example. |
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