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Old 13 October 2021, 12:16   #101
Mathesar
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Originally Posted by Samurai_Crow View Post
You'll need to get the alternate design from someone other than me. I only know that the way DMA access works is that it activates tristate buffers on the address and data busses to shut down the CPU so the DMA device can manipulate memory independently of the CPU.
You're right. the problem is that ~AS7 is not tristated as it is driven from the HCT74.
If you are feeling experimental, this is what you could do:
  • implement a pseudo-tristate by making ~AS7 an open-collecter output. Lift pin 6 of U5 and then solder a schottky diode (BAT85 or something similar) from pin 6 to ~AS on the host connector. The diode arrow must point to pin 6 (kathode on pin6, anode to ~as to host connector). It is not pretty but this way the GVP should be able to drive ~AS as well.
  • With above mode, DMA should work with the fast $C00000 RAM disabled. To also make the $C00000 ram work do the next mod as well:
  • lift pin 10 of U8 and solder a jumper wire from pin 10 to ~as on the host connector. This will make the onboard reachable from the GVP.
Remember these are all untested mods. Especially the open-collector mode is pretty dirty and might not work. If it does work however we know what to do for the next revision
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Old 13 October 2021, 14:13   #102
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Originally Posted by Mathesar View Post
You're right. the problem is that ~AS7 is not tristated as it is driven from the HCT74.
If you are feeling experimental, this is what you could do:
  • implement a pseudo-tristate by making ~AS7 an open-collecter output. Lift pin 6 of U5 and then solder a schottky diode (BAT85 or something similar) from pin 6 to ~AS on the host connector. The diode arrow must point to pin 6 (kathode on pin6, anode to ~as to host connector). It is not pretty but this way the GVP should be able to drive ~AS as well.
  • With above mode, DMA should work with the fast $C00000 RAM disabled. To also make the $C00000 ram work do the next mod as well:
  • lift pin 10 of U8 and solder a jumper wire from pin 10 to ~as on the host connector. This will make the onboard reachable from the GVP.
Remember these are all untested mods. Especially the open-collector mode is pretty dirty and might not work. If it does work however we know what to do for the next revision

OK, for me this is more theoretical solution that actually doable.
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Old 13 October 2021, 14:17   #103
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Originally Posted by sparx View Post
I have accelerator and IDE68K working on my test board
I find the biggest issue being connectivity with the CPU socket on the motherboard
I'm prety sure that this just doesn't work with IDE board. I made some testing with two A500 computers and relocator. Every time I get it work with ordinary 68000 cpu, but with accelerator IDE just disappears.

I ques, I just put this to failed projects box. This is hobby project and I can't wait things to work out of the box.
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Old 13 October 2021, 16:23   #104
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I'm prety sure that this just doesn't work with IDE board. I made some testing with two A500 computers and relocator. Every time I get it work with ordinary 68000 cpu, but with accelerator IDE just disappears.

I ques, I just put this to failed projects box. This is hobby project and I can't wait things to work out of the box.

Just to be clear, this mod is to get DMA running when you combine this accelerator with one of the GVP SCSI side cars. Your problem is different. I do not see an immediate technical reason why this accelerator would not work with the IDE68K. I have yet to study the ABEL design but in principle it should work as the IDE68K does not do DMA.
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Old 13 October 2021, 16:46   #105
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Originally Posted by Mathesar View Post
Just to be clear, this mod is to get DMA running when you combine this accelerator with one of the GVP SCSI side cars. Your problem is different. I do not see an immediate technical reason why this accelerator would not work with the IDE68K. I have yet to study the ABEL design but in principle it should work as the IDE68K does not do DMA.
That was a answer for a Sparx how said that he had this board working with IDE68k. Some reason my board doesn't work with IDE68K. As I don't have needed skills to trobleshoot this problem, I'm just going to forget it.

Basicly, I tried this board with two HD contorollers, IDE68K and GVP HD8+.
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Old 17 October 2021, 21:48   #106
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Originally Posted by utri007 View Post
Basicly, I tried this board with two HD contorollers, IDE68K and GVP HD8+.
Before throwing it in the bin... Could you measure something for me?
What is the voltage on the J2/14MHz testpoint?
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Old 18 October 2021, 17:26   #107
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Originally Posted by Mathesar View Post
Before throwing it in the bin... Could you measure something for me?
What is the voltage on the J2/14MHz testpoint?
I don't seem to get any result from it. I took a ground from top of that capasitor.

[EDIT]

Maybe I should try to get ground some where else? What kind of voltage it should gave?

Last edited by utri007; 19 October 2021 at 10:20.
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Old 19 October 2021, 11:56   #108
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I don't seem to get any result from it. I took a ground from top of that capasitor.

[EDIT]

Maybe I should try to get ground some where else? What kind of voltage it should gave?

You should read somewhere around 2.5V ideally. The closer to 2.5V, the better your 14MHz clock is. I was thinking that maybe your card does not work with the IDE68K is because of a bad 14MHz clock.
You can also get ground from the EMC shield.
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Old 21 October 2021, 00:41   #109
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Originally Posted by Mathesar View Post
You should read somewhere around 2.5V ideally. The closer to 2.5V, the better your 14MHz clock is. I was thinking that maybe your card does not work with the IDE68K is because of a bad 14MHz clock.
You can also get ground from the EMC shield.
It was 1.6V
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Old 22 October 2021, 09:01   #110
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It was 1.6V
That is very low. I need to check my old measurements to come up with a different resistor value for the PLL. The low value of 1.6V means that the dutycycle of the clock is not 50%. This influences the timing and may thus be a reason that it does not work well with the IDE68K.
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Old 25 October 2021, 16:55   #111
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I released a video on this card yesterday. There are a fair few comments from people asking were to get one, I don't suppose anyone is building them at present or knows of someone who is?

One other question that's getting asked is, why is the fast ram mapped to the slow ram address space?

I don't suppose anyone could provide an answer to this and using small words so I can understand lol.
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Old 25 October 2021, 19:21   #112
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I released a video on this card yesterday. There are a fair few comments from people asking were to get one, I don't suppose anyone is building them at present or knows of someone who is?

One other question that's getting asked is, why is the fast ram mapped to the slow ram address space?

I don't suppose anyone could provide an answer to this and using small words so I can understand lol.

Oh thats you! Great video and love your channel too


I was surprised at how much of a boost this gives. Its just a shame there isnt more RAM (even just 4MB) and IDE
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Old 25 October 2021, 21:00   #113
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Oh thats you! Great video and love your channel too


I was surprised at how much of a boost this gives. Its just a shame there isnt more RAM (even just 4MB) and IDE

Yep that's me, glad to hear you enjoy the channel.

It certainly is a nice card and performs a lot better than I was expecting.

I'm going to build the ide68k to sit under it and I'm hoping it works with a trap door chip ram mod. If I can get 1mb chip and the 1mb on this it'll be enough.
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Old 25 October 2021, 22:14   #114
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One other question that's getting asked is, why is the fast ram mapped to the slow ram address space?
I could quest that is so, because slow fast area is rarely used and leaves whole 8mb zorro II area free.
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Old 25 October 2021, 23:48   #115
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I could quest that is so, because slow fast area is rarely used and leaves whole 8mb zorro II area free.
I thought this card didn't work with an 8mb fast ram expansion.
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Old 26 October 2021, 09:20   #116
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One other question that's getting asked is, why is the fast ram mapped to the slow ram address space?

I don't suppose anyone could provide an answer to this and using small words so I can understand lol.
For this project, it is by far the best choice, technically.

The kickstart automatically detects ram in this area (up to 1.75MB with
3.1 ROM),and adds it to the memory pool before boot. If this was not the case, and you had to add the memory during boot, some stuff would go into chip-ram, which is slower.

Also, this ram is real fast-ram as it is implemented correctly on the cpu side in this case. It would only be slow if put it behind Agnus, in the trapdoor, like with regular 0.5MB cards.
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Old 26 October 2021, 12:38   #117
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For this project, it is by far the best choice, technically.

The kickstart automatically detects ram in this area (up to 1.75MB with
3.1 ROM),and adds it to the memory pool before boot. If this was not the case, and you had to add the memory during boot, some stuff would go into chip-ram, which is slower.

Also, this ram is real fast-ram as it is implemented correctly on the cpu side in this case. It would only be slow if put it behind Agnus, in the trapdoor, like with regular 0.5MB cards.
Thanks for the explanation.
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Old 28 October 2021, 20:58   #118
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Originally Posted by Glen M View Post
I released a video on this card yesterday. There are a fair few comments from people asking were to get one, I don't suppose anyone is building them at present or knows of someone who is?

One other question that's getting asked is, why is the fast ram mapped to the slow ram address space?

I don't suppose anyone could provide an answer to this and using small words so I can understand lol.
Great video and I am glad you like the card!
Your comment about it being the perfect Dread accelerator made me smile. It could have been back in the day right? Sold as a bundle? I would have certainly wanted it for Sinterklaas back then!

Quote:
For this project, it is by far the best choice, technically.

The kickstart automatically detects ram in this area (up to 1.75MB with
3.1 ROM),and adds it to the memory pool before boot. If this was not the case, and you had to add the memory during boot, some stuff would go into chip-ram, which is slower.
Spot on Somewhere along the project I had the idea to do some tricks with the address lines to relocate the trapdoor RAM to $D00000. This way the trapdoor RAM would be added to the system memory instead of overruled. This would give you 1.5MB of ranger RAM of which only the first 1MB would be really fast. It costed too much logic though.

Last edited by Mathesar; 28 October 2021 at 21:44.
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Old 28 October 2021, 21:34   #119
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Originally Posted by utri007 View Post
It was 1.6V
You might try to increase the value of resistor R3 to get the dutycycle closer to 50%. Say, 5K6 or 6K8? Maybe it fixes the incompatibility with the IDE68K.
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Old 29 October 2021, 11:31   #120
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Originally Posted by Glen M View Post
I'm going to build the ide68k to sit under it and I'm hoping it works with a trap door chip ram mod. If I can get 1mb chip and the 1mb on this it'll be enough.

I hear varying reports about compatbility with the IDE68K.
It works fine though with the trap door chip ram mod. (I did the same )
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