FPGA based A500 accelerator

[FREEMILK]

Awesome ....!!!!!?

[kipper2k]

just need to show it again, luvly!

[indigolemon]

That is sweet

[amiman99]

Nice, How is the expected performance?

[mkstr]

Originally Posted by amiman99

Nice, How is the expected performance?

I've had it pushing close to 20000 SysInfo Dhyrstones on the prototype, although I would probably dial it back a bit from there for production to ensure stability. The production could be less, could be more (depends on routing on the FPGA, and also the DRAM latency is different because the eval board has DDR3 on it).

Now that we are nearly ready to press the button on some boards I need to find the time to get back to the prototype for example to sort out a bootloader, so I will post some updated performance numbers when I do that.

[utri007]

Originally Posted by mkstr

I've had it pushing close to 20000 SysInfo Dhyrstones on the prototype, although I would probably dial it back a bit from there for production to ensure stability. The production could be less, could be more (depends on routing on the FPGA, and also the DRAM latency is different because the eval board has DDR3 on it).

Now that we are nearly ready to press the button on some boards I need to find the time to get back to the prototype for example to sort out a bootloader, so I will post some updated performance numbers when I do that.

Looks nice simple board. I'm interested. I ques compatibility is a priority with this? Not adding new stuff and integrated peripherals?

[kipper2k]

Originally Posted by utri007

Looks nice simple board. I'm interested. I ques compatibility is a priority with this? Not adding new stuff and integrated peripherals?

quote from Mikes earlier post... "There is still a bit of routing to finish off, but nothing major.

Given the form-factor the hope is that this will be applicable to all of the 16-bit Amigas including the CDTV, and also possibly the Atari ST and classic Mac with some tweaks.

The final board will have either 128MB or 256MB of DDR2 SDRAM (price difference to be determined). Micro SD slot is on there, and there is a high speed serial bus for potential add-ons.

Should be able to update with pricing soon.

.
Mike"

a high speed serial bus can add a few things

[Heywood]

I think being able to squeeze this into the profile of a 68k is an awesome achievement and I hope to obtain one if you go to production!

Nice work quite exciting to see what you have done since the last update.

[manmax]

awesome !!! Mike you are a genius !

From 1st post of this topic i hope i'll get one from first batch.
form factor is lovely and performance seems very very good.

What about hard disk speed ? is there any improvements since last screenshots ?

[Shadowfire]

I'm kind of confused. How are you dealing with the 5V level shifting? I'm not aware of any BGA mount devices for which this isn't an issue. Are there level shifters on the back of the board, or are you following down the TFA path and saying "I don't care if the IC self destructs"?

[kipper2k]

Originally Posted by Shadowfire

I'm kind of confused. How are you dealing with the 5V level shifting? I'm not aware of any BGA mount devices for which this isn't an issue. Are there level shifters on the back of the board, or are you following down the TFA path and saying "I don't care if the IC self destructs"?

level shifters are there on the underside, i havent seen a pic of the underside but they def there, the design is based on Mikes initial blog layout.

[Eriond]

Very nice board, indeed. That's how a proper accelerator should look like!
What layer count did you end up with?
If you're aiming to do high-speed serial over std. pin headers (or even HD ones as the one in your rendering), they may pose an obstacle. Speaking from experience, I would suggest switching to something else that is cheap and specifically made for the task. A std SATA connector for instance. And have an option for LVDS istead of single-ended. That will guarantee much higher transfer rates.
Still, very nicely done. I'm impressed.

[b0lt-thrower]

Hey man, don't sweat the feature creep...if this bad boy speeds up dark horse titles like Legends of Valour, Wing Commander (ECS), A-10 Tank Killer!, Stellar 7, Nova 9, and so on, then as far as I'm concerned you've got a winner.

[utri007]

Originally Posted by kipper2k

Hehe, A thing of beauty, Awesome stuff!!

Is there any estimated release date? month? year?

20 mips is about a 68040 wich is enough 99,5% of Amiga games and most of 3D etc games.

[kulamario]

This project I'll be open source?

[kipper2k]

Originally Posted by kulamario

This project I'll be open source?

from an earlier post by Mike...

http://eab.abime.net/showpost.php?p=...&postcount=155

also i believe there are 8 layers, not sure

[Lemaru]

This looks awesome. Will definitely be adding one to my collection to replace the Vampire in my A600. Just hope the pricing is nowhere near the Vamp prices.

Good work

[mkstr]

Just picking up on some of the questions above:

- SDIO IDE performance will not improve much as Gayle emulation because the bottleneck is the motherboard bus (not that I can remember where we were with numbers, but there isn't really anything to optimise there). Where it could be improved is with the addition of a DMA-capable mode (with driver obviously). This won't be there on launch but my intention is that it will be possible to update the FPGA bitstream without any special tools.
- Level shifters are underneath. There is no skimping on the design. It's an 8-layer board with double-sided SMT.
- The serial bus is underneath on an FFC connector. It is differential and has three data pairs and one clock pair. It's mainly for my own dev use but you never know.
- Release date - realistically I think January. There is a slim chance it could be ready before but I still have some more work to do on the logic and I'm pretty busy right now. There are also supply-chain problems in the industry at the moment with long lead times on a lot of components and the stocking disties out of stock of many parts. I haven't checked if anything on this is affected yet.
- Pricing - waiting on quotes from the assembly house. Will update soon. I do need to try to get a handle on levels of interest so once I have prices I will set up some sort of registration page.

Regarding open-source: As I've said before it will not be fully open source at least from day one because of the significant NRE cost that needs to be recouped. I would expect to release a subset of the HDL at some point, and possibly all of it eventually. Clearly this board would make a nice general purpose, 5V tolerant, breadboardable FPGA dev board so if there is interest for "alternative uses" that can be factored in to my volume estimates then please let me know.

Mike

[Promilus]

Opensource only makes sense if there's ample amount of ppl willing to support project. Let's see how many commits has TG68 source code since it was published... ahhh, yeah, as expected. Opensource means nothing without contributors! And I'm fairly confident many ppl asking for sources are just leechers ... to feed on original work without adding anything to it.

[kipper2k]

Originally Posted by Promilus

Opensource only makes sense if there's ample amount of ppl willing to support project. Let's see how many commits has TG68 source code since it was published... ahhh, yeah, as expected. Opensource means nothing without contributors! And I'm fairly confident many ppl asking for sources are just leechers ... to feed on original work without adding anything to it.

Agreed, This HW is well beyond the scope of people wanting to create their own boards. Everyone wants to have open source but most are either unwilling or unable to do anything with it except clone the HW. I know Mike has put in a lot of manhours working on this project and having the capability to use this in most all 68K computers/consoles is awesome. It has an excellent dev value for people that have the smarts to further develop it for other or improved usage