Assembly Code on other CPU's

[rcman]

Hi,

One thing I always liked about Amiga Assembler was the ability to move multiple registers to the stack with one command.

A lot use push and pop which I find annoying. Is there any modern processors that do that now?

Thanks
RC

[phx]

PowerPC has

lmw

and

stmw

to load/store multiple words from/to registers. But you cannot pick the registers individually, as you can with m68k. You can only specify the start-register. Then all registers up to r31 will be read/written.

[Thomas Richter]

Originally Posted by rcman

A lot use push and pop which I find annoying. Is there any modern processors that do that now?

The probable reason why modern processors avoid offering such an instruction is that its handling in case of access errors is quite tricky. Consider that you move multiple registers to memory and cross a page boundary. In such a case, the MMU would trigger an instruction in the middle of the pushed registers, one part being written, the other not. Now, if the Os repairs the page, it would need to start this instruction quite in the middle of the instruction...


The 68k family solves that in different ways. The 68030 and below stores rather extensive state information that allows restarting an instruction quite in its middle. The 68040 and onwards compute how many bytes such an instruction would populate, and then checks whether any of of the addresses touched by the instruction would cause a page exception, and then triggers the exception upfront without writing any bytes.


The latter of course does not work if the access error is a physical page fault, i.e. the RAM or some other system component refuses to accept the written bytes. In such a csae, the CPU is "stuck" and can only rerun the instruction, thus causing "double writes", which is probably not what you want if the target address belongs to an I/O device and not physical memory.


IOWs, instructions of this type are quite a headache for system designers, and there are reasons why they are not so popular.

[Dunny]

x86 has pushad and popad (push/pop all dwords) which sends all the 32 bit registers to the stack and back in one op. Does that count?

[Karlos]

@Thor

I'd never really thought about that (page boundary crossing for movem). Presumably not an issue for 040 move16 due to the alignment requirement meaning it can never span a boundary, it's always one one side or the other.

[Bruce Abbott]

You might be interested to know that the MC6809 also had this feature. It can also optionally push/pull the condition code register and PC at the same time.

6809 INSTRUCTION SET

[mschulz]

ARM working in 32-bit mode features LDM and STM instructions which allow to load/store multiple registers in the manner known from m68k. Even better, since PC register can be accessed this way, the STM can be used to push, among other registers, return address on the stack and LDM can restore registers and load return address into PC register.

On the contrary, aarch64 can only load/store pair of registers with single instruction.