02 February 2013, 20:19 | #1 |
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Assembler that generates all M68k opcodes
Hello, for curiosity and for the sake of explanation of the relationship between assembly language and machine code, I would like to know if there are Amiga assemblers that allow to generate all m68k opcodes.
It seems to me that ASM-One (at least v 1.4x) does not generate some of them, for instance ADD #im, Dx (ASM-One "optimize" it with ADDI #im, Dx). What about PhxAss, Devpac, vasm? |
02 February 2013, 22:29 | #2 |
move.l #$c0ff33,throat
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It's the other way 'round, ASM-One allows you to write the less strict add #im,x instruction (which does not exist) and automatically translates it to the correct addi instruction. It is not any kind of optimisation, it actually is just support for lazy coders!
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03 February 2013, 13:51 | #3 | |
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03 February 2013, 14:32 | #4 |
move.l #$c0ff33,throat
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ADD #IM,DX = ADDI #IM,DX
Strictly speaking, ADD #IM,DX is not a valid instruction (i.e. does not exist) but most assemblers handle it automatically since it is clear that an immediate value should be added. |
03 February 2013, 17:51 | #5 | |
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ADDI.W #$1234,D0 -> 0640 1234 If destination is a data register then there is ADD #IM,Dx AFAIK |
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03 February 2013, 19:12 | #6 |
move.l #$c0ff33,throat
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You are correct, add.x #IM,Dx is indeed allowed, I checked the reference manual. It's somewhat ambiguous though IMHO.
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05 February 2013, 10:08 | #7 | |
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Indeed, the only redundancies I have discovered up to now, are all related to the xxxI variants using a data register as destination operand: ADD # , Dx / ADDI # , Dx SUB # , Dx / SUBI # , Dx CMP # , Dx / CMPI # , Dx. AND# , Dx / ANDI # , Dx. OR # , Dx / ORI # , Dx. In contrast, there are no redundancied between ADD/ADDA, SUB/SUBA, etc. Well, another one is that you can use MOVEM to copy just 1 register, but I regard this as anavoidable. Please, let me know if you know others. |
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05 February 2013, 10:10 | #8 |
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05 February 2013, 16:14 | #9 | |
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Vasm's 68k backend supports all known 68000-68060, 68851, 6888x, CPU32 and ColdFire V2-V4e instructions. I remember just one ambiguous instruction: PFLUSHA. It exists for 68030, 68851, 68040 and 68060. The 68040/060 version has a different opcode, so the resulting code depends on the current cpu options. |
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05 February 2013, 18:31 | #10 | |||
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06 February 2013, 09:02 | #11 | ||
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I agree that it's almost useless to have both, but what I mean with the term "redundant" instruction is two different opcodes that have exactly the same semantics, for whatever values of the operands. I agree on your comment Quote:
Has PhxAss the same behavior, if you remember? Last edited by prowler; 06 February 2013 at 21:28. Reason: Back-to-back posts merged. |
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06 February 2013, 09:46 | #12 |
Natteravn
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BTW, although vasm differentiates between ADD and ADDI it will still translate ADD silently into ADDI, but only then when the addressing mode doesn't exist for ADD.
It's a long time ago. But from looking at the source it seems so. It was probably also required because of reassembling. I worked closely together with Tim Rühsen in the mid-90s, who based his IRA reassembler on PhxAss. Last edited by prowler; 06 February 2013 at 21:29. Reason: Fixed quotes. |
07 February 2013, 10:37 | #13 |
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