07 June 2021, 19:17 | #1 |
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A500+ Rev 8A and 1MB ROM
Hi,
I have successfully made a 1MB ROM with extra libs for my 1200 and works great using 27c800's Can i use the 27c800 in the 500 Plus and do the same as i have tried and it won't work (Standard 512kb ROM with the 1MB_ROM file in Remus + 512kb Extended ROM with the correct header and then the files such as workbench.library and icon.library) - is there something else i need to do like jumpers? |
07 June 2021, 22:58 | #2 |
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As far as I can tell from my A500 Rev8A here this should Just Work (TM) in theory.
I.e. you should not have to set any jumpers. I don't have anything to test this, mind. |
07 June 2021, 23:11 | #3 |
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On second thought I think the chip select for the ROM may not be enabled for the extra addresses. In that case it won't work.
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08 June 2021, 02:47 | #4 | |
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Quote:
27C800) but the A500+?: https://leblogdecosmos.blogspot.com/...mo-a500-i.html https://leblogdecosmos.blogspot.com/...o-a500-ii.html Last edited by SpeedGeek; 08 June 2021 at 14:07. |
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08 June 2021, 03:01 | #5 |
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Fab, thanks for this!
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08 June 2021, 03:10 | #6 |
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The instructions in the link though are for A500 - i have the 500+ with 42PINs so do i just connect the two wires the same or just one and do i need to bend any pins?
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08 June 2021, 05:53 | #7 |
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No bending of leads or jumper wires should be needed since the 500+ has the extra address lines connected to the socket already
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08 June 2021, 14:10 | #8 |
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It appears that you need no jumper wire or bent pins for the A500+. Your problem is then most likely an incorrectly built 1MB ROM.
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08 June 2021, 15:54 | #9 |
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Thanks I will try a few more rom builds
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08 June 2021, 16:28 | #10 |
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I've tried again and the 3.1.4 1MB i have made works in winuae - with A500+ quickstart settings.
I made sure i added the 1MB file to the standard 512kb part and the correct header in the extended 512kb rom and made those with the normal setting. i then built the 1MB ROM with the arexx script in remus for 1MB ROM and performed the byteswap. It just has blank screen on my real A500+. |
08 June 2021, 17:41 | #11 |
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Tried several ROMs and still no luck - there is jp2 with 3 soldered points next to the chip - i wonder if this is something that needs looking at - i can't find any info on this anywhere - just 1mb roms for a1200 - i have done some for my a1200 too and they work perfectly (3.1.4 plus workbench.library and icon.library on the extended rom)
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08 June 2021, 18:47 | #12 |
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JP2 does not affect the ROM, it is for the Agnus highest address bit.
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08 June 2021, 19:10 | #13 | |
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Quote:
Try to find the A500+ schematic and determine if pin 1 of the 42 pin ROM socket is actually connected a high order address line (probably A19). It makes no sense at all for Commodore to use the 42 pin socket on the A500+ and then leave this address pin N/C (but it would not be their first design blunder). If you can't find the A500+ schematic, then get a DMM and do some real continuity testing (which may be a good idea anyway, even if you do find the schematic). |
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08 June 2021, 23:20 | #14 |
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Thanks - i have a schematic now so will take a look - i am wondering if anyone else has made a 1MB ROM for a 500+ but i couldn't find any details
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08 June 2021, 23:35 | #15 | |
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Quote:
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09 June 2021, 00:33 | #16 | |
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Quote:
Another test, I forgot to mention is the mirror image read test. You simply plug in the stock 512KB ROM (which is usually a mask ROM) and read the $E00000 address space with a monitor program. You should have an exact mirror image of the 512KB ROM @ $F80000. If the mirror image test is good, then it's either a ROM build problem or a high order address bit problem, but if the mirror image test is bad, then it's a completely different hardware problem. Last edited by SpeedGeek; 09 June 2021 at 00:45. |
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09 June 2021, 01:15 | #17 |
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Thinking about A19 - i have looked at the datasheets for M27C800 and Pin1 is A18 - no A19 on the chip at all
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09 June 2021, 01:25 | #18 |
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I've had a closer look at the diagram - PIN1 is A18 and PIN42 is A19 on the A500+ mobo - this would match my 27c800 that has PIN1 as A18, but the PIN 42 is NC on the 27C800 - could connecting a wire between PIN 42 on my 27C800 and PIN 35 on GARY which is A19 possibly solve the issue?
I might try this... |
09 June 2021, 01:44 | #19 |
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Please do not confuse the CPU address with the ROM address.
The CPU address starts with A1 but the ROM address starts with A0! The end result is a 1 bit offset on 16 bit ROMs and a 2 bit offset on 32 bit ROMs... |
09 June 2021, 02:14 | #20 |
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I see - i have had to order a new gary which should arrive in a few days before i try anything else now as i managed to break the pin 35 on it.
Would the offset mean i would have to connect pin1 on the rom to the pin35 on the gary? I think this is looking like it is not possible to do now - i have some 27c400 so maybe just run out a 3.1 - i would like to somehow use the ide.device file i have to be in ROM and then somehow get it to call the ide (It's a custom ide interface) |
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