How does the smc - debugger command works?

Rock'n Roll · 17 June 2021, 16:08

I search for a simple example what the smc debugger command explains.
Does the program breaks like a program breakpoint if a smc is detected?
I could not see any success. No smc is recognized.

This is a short test programm in which the branches opcode
is changed by adding 1 from $62 to $6f.

Code:

waitmouse:  
	btst	#6,$bfe001	; left mousebutton?
	bne.s	Waitmouse	
start:
	;...
	move.b #1,d1
	move.b #1,d2
	sub.b d1,d2  
;--------------------------------------------------------
bcc_:
	; branches after unsigned comparisons
	bhi.s bitset	; $62xx
	;bhs.s bitset	; $64 == bcc	
	;blo.s bitset	; $65 == bcs	
	;bls.s bitset	; $63
	; branches on flag status
	;bcc.s bitset	; $64
	;bcs.s bitset	; $65
	;bne.s bitset	; $66
	;beq.s bitset	; $67
	;bvc.s bitset	; $68
	;bvs.s bitset	; $69
	;bpl.s bitset	; $6a
	;bmi.s bitset	; $6b	
	; branches after signed comparisons
	;bge.s bitset	; $6c
	;blt.s bitset	; $6d
	;bgt.s bitset	; $6e
	;ble.s bitset	; $6f	
	;...
	nop
bitset:
	;...
	nop
exit:
	add.b #$1,bcc_	
	cmp.b #$70,bcc_
	bne start		

	rts
	end

Code:

>d pc
00021460 0839 0006 00bf e001      BTST.B #$0006,$00bfe001
00021468 66f6                     BNE.B #$f6 == $00021460 (T)
0002146A 123c 0001                MOVE.B #$01,D1
0002146E 143c 0001                MOVE.B #$01,D2
00021472 9401                     SUB.B D1,D2
00021474 6202                     BHI.B #$02 == $00021478 (T)
00021476 4e71                     NOP
00021478 4e71                     NOP
0002147A 0639 0001 0002 1474      ADD.B #$01,$00021474 [62]
00021482 0c39 0070 0002 1474      CMP.B #$70,$00021474 [62]
>d
0002148A 6600 ffde                BNE.W #$ffde == $0002146a (T)
0002148E 4e75                     RTS
...

>f 2147A
Breakpoint added.
>m 21474 1
00021474 6202 4E71 4E71 0639 0001 0002 1474 0C39  b.NqNq.9.....t.9
>smc 0
SMCD disabled
>smc 0
SMCD enabled. Break=0
>smc 1
SMCD disabled
>smc 1
SMCD enabled. Break=1
>x

after left mousebutton - debugger reopens

Code:

>d pc
00021474 6202                     BHI.B #$02 == $00021478 (F)
00021476 4e71                     NOP
00021478 4e71                     NOP
0002147A 0639 0001 0002 1474      ADD.B #$01,$00021474 [62]
00021482 0c39 0070 0002 1474      CMP.B #$70,$00021474 [62]
0002148A 6600 ffde                BNE.W #$ffde == $0002146a (F)
0002148E 4e75                     RTS
00021490 1234 5678                MOVE.B (A4,D5.W[*8],$78) == $00000078 (68020+) [00],D1
00021494 0101                     BTST.L D0,D1
00021496 0000 001e                OR.B #$1e,D0
>m 21474 1
00021474 6202 4E71 4E71 0639 0001 0002 1474 0C39  b.NqNq.9.....t.9
>fl
0: PC == 00021474 [00000000 00000000]

>g
Breakpoint 0 triggered.
Cycles: 45 Chip, 90 CPU. (V=210 H=38 -> V=210 H=83)
  D0 00000000   D1 00000001   D2 00000000   D3 00000000
  D4 00000000   D5 00000000   D6 00000000   D7 00000000
  A0 00000000   A1 00000000   A2 00000000   A3 00000000
  A4 00000000   A5 00000000   A6 00000000   A7 00C63400
USP  00C63400 ISP  00C64400
T=00 S=0 M=0 X=0 N=0 Z=1 V=0 C=0 IMASK=0 STP=0
Prefetch 4e71 (NOP) 6302 (Bcc) Chip latch 00000000
00021474 6302                     BLS.B #$02 == $00021478 (T)
Next PC: 00021476
>g
Breakpoint 0 triggered.
Cycles: 44 Chip, 88 CPU. (V=210 H=83 -> V=210 H=127)
  D0 00000000   D1 00000001   D2 00000000   D3 00000000
  D4 00000000   D5 00000000   D6 00000000   D7 00000000
  A0 00000000   A1 00000000   A2 00000000   A3 00000000
  A4 00000000   A5 00000000   A6 00000000   A7 00C63400
USP  00C63400 ISP  00C64400
T=00 S=0 M=0 X=0 N=0 Z=1 V=0 C=0 IMASK=0 STP=0
Prefetch 4e71 (NOP) 6402 (Bcc) Chip latch 00000000
00021474 6402                     BCC.B #$02 == $00021478 (T)
Next PC: 00021476
>g
Breakpoint 0 triggered.
Cycles: 44 Chip, 88 CPU. (V=210 H=127 -> V=210 H=171)
  D0 00000000   D1 00000001   D2 00000000   D3 00000000
  D4 00000000   D5 00000000   D6 00000000   D7 00000000
  A0 00000000   A1 00000000   A2 00000000   A3 00000000
  A4 00000000   A5 00000000   A6 00000000   A7 00C63400
USP  00C63400 ISP  00C64400
T=00 S=0 M=0 X=0 N=0 Z=1 V=0 C=0 IMASK=0 STP=0
Prefetch 4e71 (NOP) 6502 (Bcc) Chip latch 00000000
00021474 6502                     BCS.B #$02 == $00021478 (F)
Next PC: 00021476
>

StingRay · 17 June 2021, 18:26

You need to enable memory watchpoints, check this thread, it should answer your questions regarding the SMC command.

Rock'n Roll · 18 June 2021, 08:19

Thanks, StingRay. It works.

I put a memwatchpoint:
>w 0 0 80000 none

then:

Code:

Breakpoint 0 triggered.
  D0 00000000   D1 00000001   D2 00000001   D3 00000000
  D4 00000000   D5 00000000   D6 00000000   D7 00000000
  A0 00000000   A1 00000000   A2 00000000   A3 00000000
  A4 00000000   A5 00000000   A6 00000000   A7 00C63400
USP  00C63400 ISP  00C64400
T=00 S=0 M=0 X=0 N=0 Z=0 V=0 C=0 IMASK=0 STP=0
Prefetch 6202 (Bcc) 9401 (SUB) Chip latch 00000000
00023B3E 9401                     SUB.B D1,D2
Next PC: 00023b40
>g
SMC at 00023B40 - 00023B41 (1) from 00023B46
Cycles: 41 Chip, 82 CPU. (V=105 H=36 -> V=105 H=77)
  D0 00000000   D1 00000001   D2 00000001   D3 00000000
  D4 00000000   D5 00000000   D6 00000000   D7 00000000
  A0 00000000   A1 00000000   A2 00000000   A3 00000000
  A4 00000000   A5 00000000   A6 00000000   A7 00C63400
USP  00C63400 ISP  00C64400
T=00 S=0 M=0 X=0 N=0 Z=0 V=0 C=0 IMASK=0 STP=0
Prefetch 6302 (Bcc) 9401 (SUB) Chip latch 00000000
00023B3E 9401                     SUB.B D1,D2
Next PC: 00023b40
>d 23B40 1
00023B40 6302                     BLS.B #$02 == $00023b44 (F)
>

Rock'n Roll · 18 June 2021, 20:49

Maybe this thread would be better in winuae.support
but now I ask my questions here:

First, I get no reaction on this commands:

Code:

mg <address>          Memory dump starting at <address> in GUI.		; no reaction
dg <address>          Disassembly starting at <address> in GUI.		; no reaction
rc					  Show CPU instruction or data cache contents.	; no reaction
rcd																	; no reaction
(rc,rcd the same output on A1200 configuration ?)

And this command shows always the complete list:

Code:

i [<addr>]            Dump contents of interrupt and trap vectors.
							; this is only i but not for instance i 6c

Now I need (wish) an explanation or simple example for following debugger commands:
Maybe also a link to an old thread would help.

Code:

b                     Step to previous state capture position.
I <custom event>      Send custom event string

di <mode> [<track>]   Break on disk access. R=DMA read,W=write,RW=both,P=PIO.
						Also enables level 1 disk logging.   
did <log level>       Enable disk logging.

wd [<0-1>]            Enable illegal access logger. 1 = enable break.
il [<mask>]           Exception breakpoint.

If I want copy eg the content of the color registers. This is difficult, because:

Code:

>e ; shows always the complete list
000 BLTDDAT     0000    100 BPLCON0     0200
002 DMACONR     03F0    102 BPLCON1     0000
004 VPOSR       8000    104 BPLCON2     0024
006 VHPOSR      0007    106 BPLCON3     0C00

better would be:

Code:

>e [<address>] [<lines>]	
>e 180 16					; eg for color registers

Or, why is this not shown?

Code:

>m dff000
00DFF000 **** **** **** ****Custom chipset* ****  ****************
00DFF010 **** **** **** ****Custom chipset* ****  ****************   

>d dff000					; ok that makes not sense...
00DFF000 ffff                     ILLEGAL
00DFF002 03f0 8000                BSET.B D1,(A0,A7.L[*8],$ff) == $00c633ff (68020+) [00]
00DFF006 0007 ffff                OR.B #$ff,D7
00DFF00A 6807                     BVC.B #$07 == $00dff013 (T)

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17 June 2021, 18:26	#2
StingRay move.l #$c0ff33,throat Join Date: Dec 2005 Location: Berlin/Joymoney Posts: 6,863	You need to enable memory watchpoints, check this thread, it should answer your questions regarding the SMC command.

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