Tinkering with a 68hc000 in an A500 - Page 2

Yulquen74 · 02 July 2015, 11:04

PM sent.

mc68k · 04 July 2015, 07:09

A quick status report:

Amiga 500 28 MHz accelerator with 8 MB DRAM

http://amigaprj.blogspot.com/2015/07...with-dram.html

hooverphonique · 06 July 2015, 11:14

what's the glue logic/dram controller implemented in? CPLD? FPGA?

mc68k · 06 July 2015, 11:15

Cpld, xc9572

alex68 · 21 January 2016, 17:44

Perhaps the 68000 reaches 50 MHz? Greetings

PR77 · 20 February 2018, 20:59

@Yulquen74,

How did you get on with your 68HC000 accelerator project?

mc68k · 21 February 2018, 05:47

Here are the results:

http://irixlabs.com/hc508

PR77 · 21 February 2018, 06:26

Wow. Super impressive! Great work. Closed source?

Yulquen74 · 22 March 2018, 19:46

PR77: Well, I did sort of finish it, meaning I got the features I wanted for my A500+/A590 combo. It only has cpu and memory, no ide controller (like mc68k's nice board and many others), as I insist on keeping my beloved A590 with scsi for my A500+.

I threw together a quick (flickery) vid showing its features:

[ Show youtube player ]

If I were to improve it, I would most certainly move to newer Xilinx CPLD, which everybody else seems to use (I used ATF1508 and WinCUPL) and DRAM (I used some low cost SRAM which is sadly no longer in production), but for now I will stick with it as it works fine for me.

malko · 22 March 2018, 20:59

Quote:

Originally Posted by mc68k

Here are the results:
http://irixlabs.com/hc508

What you have done is really impressive !

I don't understand everything that has been done here but did enjoy reading this thread.

4pLaY · 22 March 2018, 21:00

I have one of Yulquen74`s card in one of my A500+ machines, works great

.

That is one flickering video you created ;-).

PR77 · 26 March 2018, 21:06

@ Yulquen74, Wow impressive! Do you have it clocked faster than 50MHz?

I too was thinking about putting the RAM on the expansion side of the CPU as this is more "natural" for the Address and Data lines. I might experiment this this with a placement study. I have nearly finished Rev 2 of my design (https://github.com/PR77) which has been a bit slow due to a time diversion from my Amiga work.

What is the card you have next to the trap door memory expansion? Ethernet interface?

Cheers!

Yulquen74 · 27 March 2018, 10:10

PR77: It is clocked at 66 MHz, with 1 wait state for fastram / fastrom accesses.
I needed to add a fan because at this speed, the CPLD gets so hot that it becomes unstable otherwise.

The card is a Mikrotik router, which has has a linux operating system and is highly versatile.

I use it for internet access, and I also have an FTP server there, which you see me connect to and download files from in the video, through the internal plipbox interface.

PR77 · 27 March 2018, 12:33

68HC000 @ 66MHz, who would have thought! Have you implemented FastROM within the CPLD or does a helper application copy a ROM image to FastRAM, set a CPLD Flag and reset the Amiga?

Yulquen74 · 27 March 2018, 20:39

I have created a small tool in assembly which I can use to control clock frequency and fastrom stuff, I run it during boot as shown in the video, I also show its help text in the video.

The way I use it, I copy the kickstart to 0xe00000 RAM, then turn of all interrupts and
set a bit in CPLD that routes ROM accesses to same addresses in RAM space, and then copy it to the ROM space in fast RAM. I also set a bit to write protect that same RAM.

Later I use addmem command to add the 0xe00000 RAM to the memory pool, together with all the rest of the ram blocks (shown in the video). As long as the bit is set, the program can skip the rom copy stuff during startup. It should be said that I got help from some individuals in this forum to create a fast rom copy routine in assembly.

If I invoke a 2 second reset, a binary counter in CPLD resets all config bits to default value.

PR77 · 28 March 2018, 20:29

Great work! I will have a more closer look at the video- with your description it will make a lot more sense. I look forward to resuming my Rev 2 design as soon as some spare time open up!

PR77 · 11 April 2018, 09:14

@ Yulquen74, I was watching the video in more detail (and also looking on eBay for an A590

) and have an additional question regarding AutoConfig. As the A500 has a permanently grounded /CONFIG_OUT on the expansion connector I can't see how you would AutoConfig the A590 _AND_ your accelerator FastMem. Does your accelerator FastMem simple not support AutoConfig (I guess you have prioritised your A590)?

Yulquen74 · 12 April 2018, 07:52

PR77: Yes, I prioritized my A590 for autoconfig. I did not really think autoconfig was
needed for my board for several reasons:

- The fast-mem at 0xc00000 is added automatically by kickstart, and thus I have fastmem available at boot.
- I wanted more memory than the usual 8MB Z2 + ranger blocks, and would need addmem anyway to add those extra bits the correct way. The largest memory block is almost 10MB in my setup, and that would be impossible with autoconfig of memory.

PR77 · 12 April 2018, 08:50

Quote:

Originally Posted by Yulquen74

PR77: Yes, I prioritized my A590 for autoconfig. I did not really think autoconfig was
needed for my board for several reasons:

- The fast-mem at 0xc00000 is added automatically by kickstart, and thus I have fastmem available at boot.
- I wanted more memory than the usual 8MB Z2 + ranger blocks, and would need addmem anyway to add those extra bits the correct way. The largest memory block is almost 10MB in my setup, and that would be impossible with autoconfig of memory.

Thanks for the clarification.

E-Penguin · 12 April 2018, 10:51

Do you use the 2Mb on the A590? I'm after something similar for my A500+/A590. Are you selling them?

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02 July 2015, 11:04	#21
Yulquen74 Registered User Join Date: May 2013 Location: Kleppe / Norway Posts: 253	PM sent.

04 July 2015, 07:09	#22
mc68k Registered User Join Date: Jan 2015 Location: EU Posts: 27	A quick status report: Amiga 500 28 MHz accelerator with 8 MB DRAM http://amigaprj.blogspot.com/2015/07...with-dram.html

06 July 2015, 11:14	#23
hooverphonique ex. demoscener "Bigmama" Join Date: Jun 2012 Location: Fyn / Denmark Posts: 1,624	what's the glue logic/dram controller implemented in? CPLD? FPGA?

06 July 2015, 11:15	#24
mc68k Registered User Join Date: Jan 2015 Location: EU Posts: 27	Cpld, xc9572

21 January 2016, 17:44	#25
alex68 Registered User Join Date: Jan 2016 Location: Belgium Posts: 82	Perhaps the 68000 reaches 50 MHz? Greetings

20 February 2018, 20:59	#26
PR77 Registered User Join Date: Oct 2017 Location: Germany Posts: 193	@Yulquen74, How did you get on with your 68HC000 accelerator project?

21 February 2018, 05:47	#27
mc68k Registered User Join Date: Jan 2015 Location: EU Posts: 27	Here are the results: http://irixlabs.com/hc508

21 February 2018, 06:26	#28
PR77 Registered User Join Date: Oct 2017 Location: Germany Posts: 193	Wow. Super impressive! Great work. Closed source?

22 March 2018, 19:46	#29
Yulquen74 Registered User Join Date: May 2013 Location: Kleppe / Norway Posts: 253	PR77: Well, I did sort of finish it, meaning I got the features I wanted for my A500+/A590 combo. It only has cpu and memory, no ide controller (like mc68k's nice board and many others), as I insist on keeping my beloved A590 with scsi for my A500+. I threw together a quick (flickery) vid showing its features: [ Show youtube player ] If I were to improve it, I would most certainly move to newer Xilinx CPLD, which everybody else seems to use (I used ATF1508 and WinCUPL) and DRAM (I used some low cost SRAM which is sadly no longer in production), but for now I will stick with it as it works fine for me.

22 March 2018, 21:00	#31
4pLaY www.resistance.no Join Date: Jun 2008 Location: Norway Age: 43 Posts: 200	I have one of Yulquen74`s card in one of my A500+ machines, works great . That is one flickering video you created ;-).

26 March 2018, 21:06	#32
PR77 Registered User Join Date: Oct 2017 Location: Germany Posts: 193	@ Yulquen74, Wow impressive! Do you have it clocked faster than 50MHz? I too was thinking about putting the RAM on the expansion side of the CPU as this is more "natural" for the Address and Data lines. I might experiment this this with a placement study. I have nearly finished Rev 2 of my design (https://github.com/PR77) which has been a bit slow due to a time diversion from my Amiga work. What is the card you have next to the trap door memory expansion? Ethernet interface? Cheers!

27 March 2018, 10:10	#33
Yulquen74 Registered User Join Date: May 2013 Location: Kleppe / Norway Posts: 253	PR77: It is clocked at 66 MHz, with 1 wait state for fastram / fastrom accesses. I needed to add a fan because at this speed, the CPLD gets so hot that it becomes unstable otherwise. The card is a Mikrotik router, which has has a linux operating system and is highly versatile. I use it for internet access, and I also have an FTP server there, which you see me connect to and download files from in the video, through the internal plipbox interface.

27 March 2018, 12:33	#34
PR77 Registered User Join Date: Oct 2017 Location: Germany Posts: 193	68HC000 @ 66MHz, who would have thought! Have you implemented FastROM within the CPLD or does a helper application copy a ROM image to FastRAM, set a CPLD Flag and reset the Amiga?

27 March 2018, 20:39	#35
Yulquen74 Registered User Join Date: May 2013 Location: Kleppe / Norway Posts: 253	I have created a small tool in assembly which I can use to control clock frequency and fastrom stuff, I run it during boot as shown in the video, I also show its help text in the video. The way I use it, I copy the kickstart to 0xe00000 RAM, then turn of all interrupts and set a bit in CPLD that routes ROM accesses to same addresses in RAM space, and then copy it to the ROM space in fast RAM. I also set a bit to write protect that same RAM. Later I use addmem command to add the 0xe00000 RAM to the memory pool, together with all the rest of the ram blocks (shown in the video). As long as the bit is set, the program can skip the rom copy stuff during startup. It should be said that I got help from some individuals in this forum to create a fast rom copy routine in assembly. If I invoke a 2 second reset, a binary counter in CPLD resets all config bits to default value.

28 March 2018, 20:29	#36
PR77 Registered User Join Date: Oct 2017 Location: Germany Posts: 193	Great work! I will have a more closer look at the video- with your description it will make a lot more sense. I look forward to resuming my Rev 2 design as soon as some spare time open up!

11 April 2018, 09:14	#37
PR77 Registered User Join Date: Oct 2017 Location: Germany Posts: 193	@ Yulquen74, I was watching the video in more detail (and also looking on eBay for an A590 ) and have an additional question regarding AutoConfig. As the A500 has a permanently grounded /CONFIG_OUT on the expansion connector I can't see how you would AutoConfig the A590 _AND_ your accelerator FastMem. Does your accelerator FastMem simple not support AutoConfig (I guess you have prioritised your A590)?

12 April 2018, 07:52	#38
Yulquen74 Registered User Join Date: May 2013 Location: Kleppe / Norway Posts: 253	PR77: Yes, I prioritized my A590 for autoconfig. I did not really think autoconfig was needed for my board for several reasons: - The fast-mem at 0xc00000 is added automatically by kickstart, and thus I have fastmem available at boot. - I wanted more memory than the usual 8MB Z2 + ranger blocks, and would need addmem anyway to add those extra bits the correct way. The largest memory block is almost 10MB in my setup, and that would be impossible with autoconfig of memory.

12 April 2018, 10:51	#40
E-Penguin Banana Join Date: Jul 2016 Location: Darmstadt Posts: 1,213	Do you use the 2Mb on the A590? I'm after something similar for my A500+/A590. Are you selling them?

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