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Old 23 May 2008, 20:43   #1
Toni Wilen
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Join Date: Aug 2001
Location: Hämeenlinna/Finland
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A500 logic analyzer tests

This is probably better forum than uae wishlist..

Attached is first 20 or so DMA access cycles in scanline.

Also regular A->D (70=BLTADAT, 0=BLTDDAT) blit is active at the same time (easy to see free cycles)

3C = Horizontal sync strobe (note long time between strobe and real hsync signal changing state)
Following 3 x 1FE = refresh slot (strobe is first refresh)
26 = disk DMA (x 2, 3rd slot is free. Test was enabled disk write to non-existing disk)

Everything matches 100% with diagram in HRM. (so boring.. I'd have expected some differences..)

Only problem is matching VPOSR hpos=0 position. (I'd expect it to be strobe position but it may not be exactly right)
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Old 24 May 2008, 03:09   #2
Ya' like it Retr0?
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what mischief are you upto Toni?
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Old 30 June 2008, 17:52   #3

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Location: Eksjö / Sweden
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He's making sure the science gets done, like real men do.

Yeah, would have been interesting to see any deviance from HRM, many have claimed to have experienced errors.

Either way, on limited hardware it's crucial for optimum performance to know the exact behavior, not only "how to code this to do that". One example on recent platforms is knowing exact behavior of caches and memory interfaces, now that DMA plays a smaller role.

Gonna write a thread in prb.hardware for a project now cos I finally got paid...
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