68030, 68040 and 68060 MMU support (really!)

[Toni Wilen]

68030 short (type $a) bus error stack frame. When does it generate it? If documentation is true, it seems to be quite rare situation.

"For instruction faults, when the short format frame applies, the address of the pipe stage B word is the value in the program counter plus four, and the address of the stage C word is the value in the program counter plus two." And stack frame structure diagram says "PC: Next instruction" and "Execution Unit at Instruction Boundary"

Which would mean following conditions:

It can only happen if prefetch during previous instruction faults. (PC = next)
But only if word pointed by PC (next instruction) was successfully fetched. There is no field in stack frame that contains word at PC+0 ("stage D")

-> it can only happen if first word of next instruction is at MMU page - 2 and following page is invalid. This isn't that common (due to variable instruction sizes). There must be something more because it makes no sense to create shorter (faster) stack frame for rare situation.

Does any whdload qa test generate it?

[Wepl]

It seems to be used only on write faults.
Attached a register log. Just search for A008).

[Toni Wilen]

Thanks.

So it is only generated if data write fault.

This makes sense (except documentation talking about short instruction faults..), if instruction does write at the end, PC has already been increased to beginning of next instruction which means this write happens in instruction boundary = A frame is possible.

But why does A-frame have fields for instruction pipeline stages? Perhaps it is only used internally (CPU can restore already partially decoded instruction state) and for some reason they were documented. Stack frames in register file shows following instruction's opcodes in stack frame dump. But fortunately instruction pipeline stage bits are always zero

EDIT: "Last data write" A-frames seems to work, even Amix still boots.