68k emulation questions

PiCiJi · 31 January 2011, 16:45

I have a question about address mode 110 (address register indirect with index) for 68000 emulation only. I know the 68020 uses three more address mode 110 variations. I only need the calculations of the 68000 cpu. So in winuae src (newcpu.cpp) is the implementation for all 4 modes, I assume.

Can you clarify the usage for the 68000
So bit 0 - 7 of the extension word is the signed displacement.
Bit 15 tells if it uses a_reg or d_reg for index
Bit 12, 13, 14 tells the register number 0 - 7
Bit 11 tells signed usages
Bit 8, 9, 10 shifts the contents of the used reg

My question is, are all these bits evaluated for 68000 usage only? Especially is the branch "if (dp & 0x100)" used for the 68000 usage?

Thanks in advance

Toni Wilen · 01 February 2011, 13:42

Bits 8-10 are ignored by 68000 and 68010. 68020+ selects full extension mode if bit 8 is set.

UAE has 2 extension decoding routines, one for 68000/010 and another for 68020+.

PiCiJi · 02 February 2011, 15:05

Thank you.

I think a few more questions will follow during programming.

PiCiJi · 06 February 2011, 10:30

I have red an processed interrupt exception can be interrupted by a higher level interrupt. Assumption is the interrupt bits in the status register are all reset.

1. Does that mean it can be interrupted after each bus access or I/O cycle?

2. What is happening by a lower level interrupt in between the execution of a higher one? I assume the higher one is completed and before the next opcode the lower one will be processed.

3. clears the reset exception all other pending exceptions?

4. illegal opcode and interrupt are both group 1 exceptions. Can a pending interrupt cancel the processing of an illegal opcode exception in between?

Thanks in advance

Toni Wilen · 06 February 2011, 12:48

Quote:

Originally Posted by PiCiJi

I have red an processed interrupt exception can be interrupted by a higher level interrupt. Assumption is the interrupt bits in the status register are all reset.

They don't "reset".

Quote:

1. Does that mean it can be interrupted after each bus access or I/O cycle?

Interrupt processing starts if current interrupt level (Data in CPU IPL pins) > interrupt level in SR. (Between instructions only) Very simple.

Quote:

2. What is happening by a lower level interrupt in between the execution of a higher one? I assume the higher one is completed and before the next opcode the lower one will be processed.

Yes

Quote:

3. clears the reset exception all other pending exceptions?

What do you mean by pending exceptions?

Quote:

4. illegal opcode and interrupt are both group 1 exceptions. Can a pending interrupt cancel the processing of an illegal opcode exception in between?

Illegal exception stack frame is created then interrupt starts normally.

Only CPU state is stack frames and status register. CPU does not "remember" anything

PiCiJi · 06 February 2011, 17:00

Quote:

Originally Posted by PiCiJi
I have red an processed interrupt exception can be interrupted by a higher level interrupt. Assumption is the interrupt bits in the status register are all reset.

They don't "reset".

You mean, the interrupt exception handler routine doesn't change the IR level in the status register?

Quote:

1. Does that mean it can be interrupted after each bus access or I/O cycle?

Interrupt processing starts if current interrupt level (Data in CPU IPL pins) > interrupt level in SR. (Between instructions only) Very simple.

I know. What I mean is, interrupting the interrupt handler routine. Interrupt handling takes 44 clocks. In this time a higher level interrupt could occur. The interrupt acknowledge cycle take 4 clocks. so it seems to me, that in between writing the stack frame or updating the programm counter a higher level interrupt could be recognized and the interrupt exception handler routine starts again before processing of the next opcode.

Quote:

3. clears the reset exception all other pending exceptions?

What do you mean by pending exceptions?

The reset exception take 40 clocks. In this time an interrupt from other unit like the genesis/mega drive graphic unit could occur. The interrupt is lower prioritized than reset, so the reset executes. the reset sets all interrupt bits in the status register. But maybe before starting the first opcode after reset, a pending level 7 (NMI) fires. I wonder if this is possible?

Quote:

4. illegal opcode and interrupt are both group 1 exceptions. Can a pending interrupt cancel the processing of an illegal opcode exception in between?

Illegal exception stack frame is created then interrupt starts normally.

Ok. That means the interrupt starts before the illegal exception handler is updating the program counter or prefetching?

My general understanding problem:
In opcode execution a reset, address error or bus error can interrupt or better cancel the execution of the current opcode. That seems clear to me.

But how works interruption during an exception handling?
In General can writing the stack frame be interrupted? Or can updating the program counter or prefetching within exception handling be interrupted?

andreas · 10 February 2011, 20:06

Shouldn't "Coder's Heaven" be a better place for this thread?
(Well, just pondering...)

Toni Wilen · 12 February 2011, 12:58

No interrupts can happen during CPU internal exception processing (stack frame creation etc..)

Another exception can happen during exception processing (bus or address exception)

Reset exception: no idea, Amiga can't generate reset exceptions (reset instruction does not cause reset exception)

PiCiJi · 05 March 2011, 18:13

Thanks for last info.

Division by zero and chk exceptions take 5 bus read cycles. (found in following doc)
http://oldwww.nvg.ntnu.no/amiga/MC68...timexcept.HTML

I can only count 4 bus read cycles like trap and trapv. 2 for reading the exception vector and 2 for prefetching full

Can you clear this?

Toni Wilen · 05 March 2011, 18:32

(from winuae sources, newcpu.c, result of lots of logic analyzer tests. cycle = one cpu clock cycle, 1 memory cycle = 4 clock cycles)

Address/Bus Error:

- 6 idle cycles
- write PC low word
- write SR
- write PC high word
- write instruction word
- write fault address low word
- write status code
- write fault address high word
- 2 idle cycles
- read exception address high word
- read exception address low word
- prefetch
- 2 idle cycles
- prefetch

Division by Zero:

- 6 idle cycles
- write PC low word
- write SR
- write PC high word
- read exception address high word
- read exception address low word
- prefetch
- 2 idle cycles
- prefetch

Traps:

- 2 idle cycles
- write PC low word
- write SR
- write PC high word
- read exception address high word
- read exception address low word
- prefetch
- 2 idle cycles
- prefetch

TrapV:

- write PC low word
- write SR
- write PC high word
- read exception address high word
- read exception address low word
- prefetch
- 2 idle cycles
- prefetch

CHK:

- 6 idle cycles
- write PC low word
- write SR
- write PC high word
- read exception address high word
- read exception address low word
- prefetch
- 2 idle cycles
- prefetch

Illegal Instruction:

- 2 idle cycles
- write PC low word
- write SR
- write PC high word
- read exception address high word
- read exception address low word
- prefetch
- 2 idle cycles
- prefetch

Interrupt:

- 6 idle cycles
- write PC low word
- read exception number byte from (0xfffff1 | (interrupt number << 1))
- 4 idle cycles
- write SR
- write PC high word
- read exception address high word
- read exception address low word
- prefetch
- 2 idle cycles
- prefetch

PiCiJi · 12 March 2011, 11:56

Thank you.

Like the 68k, the 65816 CPU handles interrupts after each opcode.
However, the 65816 CPU doesn't recognize an incoming interrupt during last machine cycle of executed opcode. So the interrupt is handled after the next opcode.
Is such like behavior known for the 68k?

Toni Wilen · 12 March 2011, 12:40

Yes and no. Interrupt lines has at least 1 cycle before IPL line change is detected (probably all CPUs do this to not detect spurious interrupts when lines are changing state)

But IPL latch to status register transfer is probably done in microcode because different instructions that have identical cycle usage don't always have same interrupt "delay". (I had good test case but I don't remember it anymore..)

PiCiJi · 18 February 2013, 20:27

It's been a while since last question.

i have a few problems understanding which value the program counter contains at any given time of execution.

Is the program counter incremented directly before or after a prefetch (instruction or extension word) ?

I am wondering because of instructions like dbcc. In the manual it says the pc contains the address of the instruction + 2 at the time when generating the new pc for branch. In my emulation attempt the value is the address + 4, because I am incrementing the pc after fetching a word.

Because of the prefetch cycle of the previous instruction, the pc seems to increase directly before a prefetch. That would mean fetching the first instruction word after a reset doesn't increase the pc.

Toni Wilen · 18 February 2013, 20:59

AFAIK PC is also incremented by microcode, it is not hardwired to prefetches. (68000/010 only, 68020+ is totally different)

PiCiJi · 18 February 2013, 21:55

Thank you, that explains why I couldn't find any clear information in the common manuals.

PiCiJi · 23 February 2013, 18:31

How behaves the v flag for the NBCD opcode on a 68000 cpu?

MOVE.B #$7a, D1
MOVE #$0, CCR
NBCD D1

The v-flag is seted in easy68k and according a document about undocumented opcode behaviour but not in WinUAE (emulated A500+ using Trash'M-One v1.6)

http://emu-docs.org/CPU%2068k/68knotes.txt

I have tried it on a real 68020 cpu. The v flag will not set, even it was set before. It seems set to zero always.

Toni Wilen · 23 February 2013, 19:33

Hmm.. For some reason NBCD didn't have V-flag handling, only SBCD had it. (Forgotten? Missed? I don't know, this was Bernd's code) ABCD also appears to be correct.

Note that 68040 is again different than 68020. 68040 appears to not touch V or N flag at all.

PiCiJi · 23 February 2013, 19:59

yes, ABCD and SBCD seem to be correct.

I have to inform the people from easy68k too, because the assembly from my last post sets the N flag in easy68k. It shouldn't.

Leffmann · 23 February 2013, 23:45

Quoted from the manufacturer:

X — Set the same as the carry bit.
N — Undefined.
Z — Cleared if the result is nonzero; unchanged otherwise.
V — Undefined.
C — Set if a decimal borrow occurs; cleared otherwise.

PiCiJi · 17 March 2013, 23:37

I have a question about prefetch time window.

Instructions with logic cycles (non bus cycles) like add or sub prefetch the next opcode concurrently to such a logic cycle.

Instructions like mulu or shift/rotate can have a big amount of logic cycles.

When is prefetching done?
I would assume at latest possible time, means during last 4 logic cycles.

31 January 2011, 16:45	#1
PiCiJi Registered User Join Date: Sep 2003 Location: germany Age: 45 Posts: 459	68k emulation questions I have a question about address mode 110 (address register indirect with index) for 68000 emulation only. I know the 68020 uses three more address mode 110 variations. I only need the calculations of the 68000 cpu. So in winuae src (newcpu.cpp) is the implementation for all 4 modes, I assume. Can you clarify the usage for the 68000 So bit 0 - 7 of the extension word is the signed displacement. Bit 15 tells if it uses a_reg or d_reg for index Bit 12, 13, 14 tells the register number 0 - 7 Bit 11 tells signed usages Bit 8, 9, 10 shifts the contents of the used reg My question is, are all these bits evaluated for 68000 usage only? Especially is the branch "if (dp & 0x100)" used for the 68000 usage? Thanks in advance

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01 February 2011, 13:42	#2
Toni Wilen WinUAE developer Join Date: Aug 2001 Location: Hämeenlinna/Finland Age: 49 Posts: 26,575	Bits 8-10 are ignored by 68000 and 68010. 68020+ selects full extension mode if bit 8 is set. UAE has 2 extension decoding routines, one for 68000/010 and another for 68020+.

02 February 2011, 15:05	#3
PiCiJi Registered User Join Date: Sep 2003 Location: germany Age: 45 Posts: 459	Thank you. I think a few more questions will follow during programming.

06 February 2011, 10:30	#4
PiCiJi Registered User Join Date: Sep 2003 Location: germany Age: 45 Posts: 459	I have red an processed interrupt exception can be interrupted by a higher level interrupt. Assumption is the interrupt bits in the status register are all reset. 1. Does that mean it can be interrupted after each bus access or I/O cycle? 2. What is happening by a lower level interrupt in between the execution of a higher one? I assume the higher one is completed and before the next opcode the lower one will be processed. 3. clears the reset exception all other pending exceptions? 4. illegal opcode and interrupt are both group 1 exceptions. Can a pending interrupt cancel the processing of an illegal opcode exception in between? Thanks in advance

10 February 2011, 20:06	#7
andreas Zone Friend Join Date: Jun 2001 Location: Germany Age: 50 Posts: 5,857	Shouldn't "Coder's Heaven" be a better place for this thread? (Well, just pondering...)

12 February 2011, 12:58	#8
Toni Wilen WinUAE developer Join Date: Aug 2001 Location: Hämeenlinna/Finland Age: 49 Posts: 26,575	No interrupts can happen during CPU internal exception processing (stack frame creation etc..) Another exception can happen during exception processing (bus or address exception) Reset exception: no idea, Amiga can't generate reset exceptions (reset instruction does not cause reset exception)

05 March 2011, 18:13	#9
PiCiJi Registered User Join Date: Sep 2003 Location: germany Age: 45 Posts: 459	Thanks for last info. Division by zero and chk exceptions take 5 bus read cycles. (found in following doc) http://oldwww.nvg.ntnu.no/amiga/MC68...timexcept.HTML I can only count 4 bus read cycles like trap and trapv. 2 for reading the exception vector and 2 for prefetching full Can you clear this?

05 March 2011, 18:32	#10
Toni Wilen WinUAE developer Join Date: Aug 2001 Location: Hämeenlinna/Finland Age: 49 Posts: 26,575	(from winuae sources, newcpu.c, result of lots of logic analyzer tests. cycle = one cpu clock cycle, 1 memory cycle = 4 clock cycles) Address/Bus Error: - 6 idle cycles - write PC low word - write SR - write PC high word - write instruction word - write fault address low word - write status code - write fault address high word - 2 idle cycles - read exception address high word - read exception address low word - prefetch - 2 idle cycles - prefetch Division by Zero: - 6 idle cycles - write PC low word - write SR - write PC high word - read exception address high word - read exception address low word - prefetch - 2 idle cycles - prefetch Traps: - 2 idle cycles - write PC low word - write SR - write PC high word - read exception address high word - read exception address low word - prefetch - 2 idle cycles - prefetch TrapV: - write PC low word - write SR - write PC high word - read exception address high word - read exception address low word - prefetch - 2 idle cycles - prefetch CHK: - 6 idle cycles - write PC low word - write SR - write PC high word - read exception address high word - read exception address low word - prefetch - 2 idle cycles - prefetch Illegal Instruction: - 2 idle cycles - write PC low word - write SR - write PC high word - read exception address high word - read exception address low word - prefetch - 2 idle cycles - prefetch Interrupt: - 6 idle cycles - write PC low word - read exception number byte from (0xfffff1 \| (interrupt number << 1)) - 4 idle cycles - write SR - write PC high word - read exception address high word - read exception address low word - prefetch - 2 idle cycles - prefetch

12 March 2011, 11:56	#11
PiCiJi Registered User Join Date: Sep 2003 Location: germany Age: 45 Posts: 459	Thank you. Like the 68k, the 65816 CPU handles interrupts after each opcode. However, the 65816 CPU doesn't recognize an incoming interrupt during last machine cycle of executed opcode. So the interrupt is handled after the next opcode. Is such like behavior known for the 68k?

12 March 2011, 12:40	#12
Toni Wilen WinUAE developer Join Date: Aug 2001 Location: Hämeenlinna/Finland Age: 49 Posts: 26,575	Yes and no. Interrupt lines has at least 1 cycle before IPL line change is detected (probably all CPUs do this to not detect spurious interrupts when lines are changing state) But IPL latch to status register transfer is probably done in microcode because different instructions that have identical cycle usage don't always have same interrupt "delay". (I had good test case but I don't remember it anymore..)

18 February 2013, 20:27	#13
PiCiJi Registered User Join Date: Sep 2003 Location: germany Age: 45 Posts: 459	It's been a while since last question. i have a few problems understanding which value the program counter contains at any given time of execution. Is the program counter incremented directly before or after a prefetch (instruction or extension word) ? I am wondering because of instructions like dbcc. In the manual it says the pc contains the address of the instruction + 2 at the time when generating the new pc for branch. In my emulation attempt the value is the address + 4, because I am incrementing the pc after fetching a word. Because of the prefetch cycle of the previous instruction, the pc seems to increase directly before a prefetch. That would mean fetching the first instruction word after a reset doesn't increase the pc.

18 February 2013, 20:59	#14
Toni Wilen WinUAE developer Join Date: Aug 2001 Location: Hämeenlinna/Finland Age: 49 Posts: 26,575	AFAIK PC is also incremented by microcode, it is not hardwired to prefetches. (68000/010 only, 68020+ is totally different)

18 February 2013, 21:55	#15
PiCiJi Registered User Join Date: Sep 2003 Location: germany Age: 45 Posts: 459	Thank you, that explains why I couldn't find any clear information in the common manuals.

23 February 2013, 18:31	#16
PiCiJi Registered User Join Date: Sep 2003 Location: germany Age: 45 Posts: 459	How behaves the v flag for the NBCD opcode on a 68000 cpu? MOVE.B #$7a, D1 MOVE #$0, CCR NBCD D1 The v-flag is seted in easy68k and according a document about undocumented opcode behaviour but not in WinUAE (emulated A500+ using Trash'M-One v1.6) http://emu-docs.org/CPU%2068k/68knotes.txt I have tried it on a real 68020 cpu. The v flag will not set, even it was set before. It seems set to zero always.

23 February 2013, 19:33	#17
Toni Wilen WinUAE developer Join Date: Aug 2001 Location: Hämeenlinna/Finland Age: 49 Posts: 26,575	Hmm.. For some reason NBCD didn't have V-flag handling, only SBCD had it. (Forgotten? Missed? I don't know, this was Bernd's code) ABCD also appears to be correct. Note that 68040 is again different than 68020. 68040 appears to not touch V or N flag at all.

23 February 2013, 19:59	#18
PiCiJi Registered User Join Date: Sep 2003 Location: germany Age: 45 Posts: 459	yes, ABCD and SBCD seem to be correct. I have to inform the people from easy68k too, because the assembly from my last post sets the N flag in easy68k. It shouldn't.

23 February 2013, 23:45	#19
Leffmann Join Date: Jul 2008 Location: Sweden Posts: 2,269	Quoted from the manufacturer: X — Set the same as the carry bit. N — Undefined. Z — Cleared if the result is nonzero; unchanged otherwise. V — Undefined. C — Set if a decimal borrow occurs; cleared otherwise.

17 March 2013, 23:37	#20
PiCiJi Registered User Join Date: Sep 2003 Location: germany Age: 45 Posts: 459	I have a question about prefetch time window. Instructions with logic cycles (non bus cycles) like add or sub prefetch the next opcode concurrently to such a logic cycle. Instructions like mulu or shift/rotate can have a big amount of logic cycles. When is prefetching done? I would assume at latest possible time, means during last 4 logic cycles.

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