15 July 2020, 02:40 | #1 | |
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68020 Data registers as addresses? (VASM?)
Mentioned here : http://jvaltane.kapsi.fi/amiga/howto...0x0issues.html
Quote:
Code:
move.l #x,d0 ; Allocation bytes move.l #MEMF_CHIP,d1 ; CHIP Ram jsr _LVOAllocMem(a6) ; exec -198 move.l d0,a0 move.l #0,0(a0) ; WORKS move.l #0,0(d0) ; FAILS Is it true a data register can be used as address register on 68020+ (with penalty)? If so, is it able to be used with said addressing mode? Thank you! |
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15 July 2020, 03:30 | #2 |
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Yes, 020+ new adressing modes can handle that. But it doesn't quite work the same way.
Basically, the full addressing mode is ([offset,ax or pc,index*scale],displacement) and the individual parts can be suppressed. So you do that to everything except the index, which is either ax or dx, so dx in your case, and you get ([dx]). Now what does this do? It reads a 32-bit address from memory pointed by dx (everything inside square brackets), and then adds displacement to it and it reads/writes data from/to that displaced 32-bit address. So it's kind of a double index, or in plain m68k it would be like: Code:
move.l offset(ax,rx*scale),tmp_areg move.l #0,displacement(tmp_areg) |
15 July 2020, 08:52 | #3 |
son of 68k
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If 0(d0) fails, try (d0.l) instead.
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15 July 2020, 09:52 | #4 |
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works if you invoke vasm with -m68020
vasmm68k_mot -m68020 -Fhunk -o foo foo.asm |
15 July 2020, 11:05 | #5 |
Natteravn
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Meynaf makes an important point. d0 is the index register! So when you write 0(d0) it is really (0,za0,d0.w). The address register is assumed as a0 and suppressed. The size of the index register always defaults to Word(!). Which means the MSW from your pointer in d0 will be disregarded.
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17 July 2020, 02:54 | #6 |
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Thank you all,
Absolutely clear now. Thanks a/b for the explanation on the full addressing mode. Working successfully now with suppressed or full syntax. !! As noted by phx and meynaf d0.l is absolutely key. |
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