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28 January 2019, 00:37
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#1 |
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Registered User
Join Date: Apr 2018
Location: Stockholm / Sweden
Posts: 129
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Questions regarding INT2 interrupt handling
Hi all, I have a few questions about the /INT2 interrupt pin that is available on the A500 86-pin expansion port. The INT2 pin is connected from the expansion bus to a pin on Paula.
The first question is: is INT2 edge-triggered or level-triggered? I.e. if bit INTB_PORTS is cleared from INTREQ while INT2 is still asserted (held low/at ground) will Paula set the bit INTB_PORTS in INTREQ again or not? [...] Last edited by Niklas; 28 January 2019 at 08:13. Reason: Two questions removed as they were only relevant if INT2 had been edge triggered, which it isn't. |
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28 January 2019, 07:27
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#2 |
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WinUAE developer
Join Date: Aug 2001
Location: Hämeenlinna/Finland
Age: 49
Posts: 26,570
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EXTER/PORTS interrupts are level triggered. (Clearing INTREQ bit when interrupt signal is still active: INTREQ bit gets immediately set again)
Last edited by Toni Wilen; 28 January 2019 at 08:04. |
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28 January 2019, 08:09
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#3 | |
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Registered User
Join Date: Apr 2018
Location: Stockholm / Sweden
Posts: 129
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