CPU execution on odd cycles if no Audio/Disk/Sprite DMA

[mc6809e]

I'm just wondering if it's possible with the OCS. I know the HRM says that the CPU accesses chipram on even cycles only, but I'm skeptical that this rule is absolute given that there are times Agnes must add a one cycle delay to CPU accesses at the end of certain scan lines. I realize DRAM refresh at the beginning of each scan line is going to force the CPU to use the even cycles, but if Audio/Disk/Sprite/BP DMA is turned off might there be situations where the CPU can use those odd cycles?

If the CPU can occasionally use some odd cycles, perhaps more CPU/Blitter concurrency can be achieved by using the copper to start blits at the end of the last displayable line. And any calls to exec or fast ram should be done on the first displayable line rather than on VERTB interrupt.

Can someone verify if odd cycle chipram access by the CPU is possible?

[Toni Wilen]

HRM is wrong, there are no CPU cycle restrictions. CPU can use both odd or even free cycles. (But as you said, refresh and other Agnus DMA channels usually force even cycle "alignment" sooner or later)

[Photon]

clr.l Dn or similar should be useful as pad instruction, if you want to line up with a HPOS-wait on the previous line. For non-68000 CPUs you need another strat...