Shearing at line 200?

korruptor · 14 March 2007, 16:24

Hi there,

I've just knocked up an interference circles effect in WinUAE (part of my "teach yourself assembly" program

and I've noticed that I'm getting some shearing just below the ntsc line.

This might be related to how I've implemented the effect, though. The first plane is hardware scrolled and the second plane is just blitted from the same source, into the correct position.

The shearing is only happening on my hardware scrolled plane, though.

I've read about putting in a dc.w $ffdf,$fffe in the copper list, but this on it's own makes no difference.

Can anyone give me a pointer as to what the problem is. I'm assuming it's not UAE and something to do with Pal timings, or something...

Thanks in advance

korruptor · 14 March 2007, 17:49

Er, meant to say, the source is here if anyone wants a quick look

http://kor.gazaxian.com/Interference-2.asm

Cheers

AGN · 15 March 2007, 21:54

Put on web all missing files ("Includes/CustomEquates.i", "Includes/Macros.i", "Data/rings.raw").

korruptor · 16 March 2007, 10:10

No probs, try:

http://kor.gazaxian.com/Interference.zip

I've had a reply to this problem via ADA and it looks like it's down to race conditions. I'm updating HW regs from the copper and CPU and I've not double buffered my copper list. I've also been given some other pointers for how to wait for the VBL correctly.

I'm grateful for anything else you uncover...

AGN · 16 March 2007, 14:32

You are right. In Your "wait_VBL" routine:

Code:

cmp.b #$ff, vhposr(a6)

You are waiting for line where tearing occurs, then some custom registers are touched:

Code:

move.w  #24, bpl1mod(a6)
move.b  d4, bplcon1(a6)

Solutions?

1/ Waiting for last line of NTSC might be ok. All You need is to modify bpl1mod/bplcon1 from copperlist and above code shoud touch copperlist instead of custom registers.

2/ Fixing vait_vbl
vhposr only contains first 8 bits of vertical position, missing ones are in vposr

loop:
move.l vposr(a6),d0 ; fed 2 registers at once
and.l #$1ff00,d0 ; strip all unrelated stuff, leave only 0-8 (9) bits of vpos
cmp.l #$12800,d0 ; move tearing down

ble.s loop

3/ interrupts?

korruptor · 17 March 2007, 17:41

Thanks for the reply, it's really useful.

I'm going to have a look at interrupts. I've not really read up on them, but it's pretty clear it's the way to go

Thanks for the VBL information. I'd actually just lifted the macro from some source on Aminet and not done my homework. It's still early days for my Amiga coding

Thanks again

14 March 2007, 16:24	#1
korruptor TDI Join Date: Feb 2007 Location: Blitter Town Posts: 124	Shearing at line 200? Hi there, I've just knocked up an interference circles effect in WinUAE (part of my "teach yourself assembly" program and I've noticed that I'm getting some shearing just below the ntsc line. This might be related to how I've implemented the effect, though. The first plane is hardware scrolled and the second plane is just blitted from the same source, into the correct position. The shearing is only happening on my hardware scrolled plane, though. I've read about putting in a dc.w $ffdf,$fffe in the copper list, but this on it's own makes no difference. Can anyone give me a pointer as to what the problem is. I'm assuming it's not UAE and something to do with Pal timings, or something... Thanks in advance

16 March 2007, 14:32	#5
AGN Registered User Join Date: Aug 2004 Location: Poland Posts: 142	You are right. In Your "wait_VBL" routine: Code: cmp.b #$ff, vhposr(a6) You are waiting for line where tearing occurs, then some custom registers are touched: Code: move.w #24, bpl1mod(a6) move.b d4, bplcon1(a6) Solutions? 1/ Waiting for last line of NTSC might be ok. All You need is to modify bpl1mod/bplcon1 from copperlist and above code shoud touch copperlist instead of custom registers. 2/ Fixing vait_vbl vhposr only contains first 8 bits of vertical position, missing ones are in vposr loop: move.l vposr(a6),d0 ; fed 2 registers at once and.l #$1ff00,d0 ; strip all unrelated stuff, leave only 0-8 (9) bits of vpos cmp.l #$12800,d0 ; move tearing down ble.s loop 3/ interrupts?

Similar Threads
Thread	Thread Starter	Forum	Replies	Last Post
CD-200 crashes with SX-1	th4t1guy	support.Games	2	26 June 2015 16:41
200 game cd	jimbob005	request.Old Rare Games	2	04 August 2008 08:32
200 % fps	turrican3	request.UAE Wishlist	13	30 July 2008 18:34
Moonstone for almost $200, are they serious?	Pyromania	Retrogaming General Discussion	29	13 November 2003 22:28
Almost $200 for an A500??!!! Why??	Pyromania	MarketPlace	10	10 May 2003 12:52

14 March 2007, 17:49	#2
korruptor TDI Join Date: Feb 2007 Location: Blitter Town Posts: 124	Er, meant to say, the source is here if anyone wants a quick look http://kor.gazaxian.com/Interference-2.asm Cheers

15 March 2007, 21:54	#3
AGN Registered User Join Date: Aug 2004 Location: Poland Posts: 142	Put on web all missing files ("Includes/CustomEquates.i", "Includes/Macros.i", "Data/rings.raw").

16 March 2007, 10:10	#4
korruptor TDI Join Date: Feb 2007 Location: Blitter Town Posts: 124	No probs, try: http://kor.gazaxian.com/Interference.zip I've had a reply to this problem via ADA and it looks like it's down to race conditions. I'm updating HW regs from the copper and CPU and I've not double buffered my copper list. I've also been given some other pointers for how to wait for the VBL correctly. I'm grateful for anything else you uncover...

17 March 2007, 17:41	#6
korruptor TDI Join Date: Feb 2007 Location: Blitter Town Posts: 124	Thanks for the reply, it's really useful. I'm going to have a look at interrupts. I've not really read up on them, but it's pretty clear it's the way to go Thanks for the VBL information. I'd actually just lifted the macro from some source on Aminet and not done my homework. It's still early days for my Amiga coding Thanks again

Currently Active Users Viewing This Thread: 1 (0 members and 1 guests)