17 June 2010, 23:24 | #21 |
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The CPU can write COLOR0 register (or any other custom register) every 2 CCKs (4 lowres pixels). The DMA could write COLOR0 register every CCK cycle (2 lowres pixels). With simple register address transcoding for Denise (mapping BPLxDAT registers to COLOR0) we can have 12-bit highcolour chunky (interleaved) display mode with nominal resolution of 160 pixels per line.
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18 June 2010, 08:44 | #22 |
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Thx Kalms, Yaqube,
So hardware overlay is not possible (with using Denise) - with some additional logic, inject data to one of the color registers and create video only on one particular color - it must be done outside Denise maybe with using ZD. |
18 June 2010, 12:12 | #23 | |
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18 June 2010, 15:06 | #24 |
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18 June 2010, 15:19 | #25 |
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18 June 2010, 23:14 | #26 |
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Accordingly to programmers - there is possible to do copper chunky 2x1 - 160 independent 12 bit pix on screen in 1 line - without any hardware modifications.
My question was bit different - external buffer, logic and inject buffer data as a color value to the Denise register - buffer outside CHIP bus - using only D0-D15, RGA1-RGA8 and some strobes etc |
19 June 2010, 00:11 | #27 | ||
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20 June 2010, 01:09 | #28 |
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Yaqube - not directly by changing color register value but with clever manipulation of pixels and color registers - probably also interlace is used (i suppose as a vertical oversampling) - limitations of the copper are known and i don't argue with this.
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07 November 2013, 19:47 | #29 |
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any news chaps? if the c64 can get 8-bit sound the amiga should get fancy sound too!
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07 November 2013, 20:24 | #30 | |
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I play CD quality WAV files on my A1200 in 44 khz (I always use a double scan mode), and they sound great. Other than standard DMA audio playback, it might be possible to do playback with the copper if it can control the right audio registers, but then you have a limited number of screen colors available. Simply using audio DMA is probably the most useful, and produces good quality. |
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07 November 2013, 20:37 | #31 |
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17 February 2021, 08:51 | #32 | |
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I get the explanation for the sampling rates without AUDxDSR but would have assumed they are the same with the AUDxDSR sent simultaneously. My understanding is that the DMA pointer will only be updated by Agnus after the word has already been fetched, and since the next word is earliest fetched 227 cycles later (PAL) I can't see how it can have an impact. The word is still written to AUDxDAT in the usual DMA cycles i.e. 13 for channel 0 or isn't it? |
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12 September 2021, 11:48 | #33 | |
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It seems to be Paula feature (As you already said, Agnus can't cause the delay). If internal sample length counter == 1: counter is reloaded (1 cycle delay) and then AUDxDSR DMAL bit is generated. If internal sample counter != 1: AUDxDR bit is immediately generated. This logic matches real hardware behavior in UAE. (Of course I can't be 100% sure this is exactly what happens inside Paula but it probably is close enough in |
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15 September 2021, 06:22 | #34 |
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OK, I think I understand.
Just for clarification (all statements for PAL Amigas): We have this steps in Agnus for sample counter != 1:
So the worst case is when Paula transitions back from 011 to 010 at exactly the DMA Cycle 0. Then it takes 227 cycles until the buffered signal is latched to the internal shift register and another 13 cycles until it is signaled to Agnus. That gives us 227+13 = 240 cycles or a minimum sample period of 120. And this steps in Agnus for sample counter = 1:
So the worst case is when Paula transitions back from 011 to 010 at exactly the DMA Cycle -1 = 227. Then it takes 228 cyles until the buffered AUDxDR signal is latched to the internal shift register and another 13 cycles until it is signaled to Agnus. That gives us 228+13 = 241 cycles or a minimum sample period of 120.5 => 121. Is that correct? |
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