18 December 2012, 15:08 | #1 |
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Open-source scsi device
I started to optimise/rework scsi device.
Three versions are available: for A600 (ROM 3.0+), for A1200 and for A4000 on: http://wt.exotica.org.uk/test.html At begining reworked are Init (partially) and ReadWriteData routines New version is a few fastest, especially for slower CPU's. Also perhaps one original bug is fixed for ReadWriteData routine error handling. Code:
;ReadWriteData MOVEM.L D2/D3,-(SP) ; MOVE.L D0,D2 ; MOVEQ #0,D3 ; CMP.B #4,D2 ; BEQ.S WaitForReady ;lbC002F18 TST.B D3 ; BNE.S WaitForReady ; MOVE.L $20(A5),D0 ; JSR -$13E(A6) ;WaitForReady MOVE.B $1E-Modulo(A4),D0 ; CMP.B #2,D2 ; BEQ.S lbC002F34 ; CMP.B #4,D2 ; BNE.S lbC002F46 ;lbC002F34 BTST #7,D0 ; BNE.S WaitForReady ; BTST #0,D0 ; BNE.S lbC002F4E ; error handler ??? ; BTST #3,D0 ; BEQ.S WaitForReady ;lbC002F46 MOVE.W lbW002F5C(PC,D2.W),D0 ; JMP lbW002F5C(PC,D0.W) ;lbC002F4E MOVE.B 6-Modulo(A4),$277(A2) ; MOVE.W lbW002F64(PC,D2.W),D0 ; JMP lbW002F64(PC,D0.W) ;lbW002F5C dc.w lbC002F6C-lbW002F5C ; 0 ; dc.w lbC002F7E-lbW002F5C ; 2 read data ; dc.w lbC002FF4-lbW002F5C ; 4 write data ; dc.w lbC002F6C-lbW002F5C ; 6 ;lbW002F64 dc.w lbC00307E-lbW002F64 ; dc.w lbC00307E-lbW002F64 ; dc.w lbC003072-lbW002F64 ; dc.w lbC003072-lbW002F64 ;lbC002F6C MOVE.B $1E-Modulo(A4),D0 ; BTST #7,D0 ; BNE.S lbC002F6C ;lbC002F76 MOVEQ #0,D0 ;lbC002F78 MOVEM.L (SP)+,D2/D3 ; RTS ;lbC002F7E MOVEA.L $60(A3),A1 ; read data (512 bytes) ; MOVEA.L A4,A0 ; MOVE.L A1,D1 ; BTST #0,D1 ; BNE.S lbC002FD6 ; MOVEQ #15,D0 ;lbC002F8E MOVE.W (A0),(A1)+ ; even address copy routine ; MOVE.W (A0),(A1)+ ; MOVE.W (A0),(A1)+ ; MOVE.W (A0),(A1)+ ; MOVE.W (A0),(A1)+ ; MOVE.W (A0),(A1)+ ; MOVE.W (A0),(A1)+ ; MOVE.W (A0),(A1)+ ; MOVE.W (A0),(A1)+ ; MOVE.W (A0),(A1)+ ; MOVE.W (A0),(A1)+ ; MOVE.W (A0),(A1)+ ; MOVE.W (A0),(A1)+ ; MOVE.W (A0),(A1)+ ; MOVE.W (A0),(A1)+ ; MOVE.W (A0),(A1)+ ; DBRA D0,lbC002F8E ;lbC002FB2 MOVE.L A1,$60(A3) ; MOVEA.L $6C(A3),A0 ; ADDI.L #$200,8(A0) ; ADDQ.B #1,D3 ; CMP.B $6C(A2),D3 ; BCS.S lbC002FCC ; MOVEQ #0,D3 ;lbC002FCC SUBQ.B #1,$4A(A3) ; BNE.W lbC002F18 ; BRA.S lbC002F76 ;lbC002FD6 MOVEQ #$7F,D0 ; odd address copy routine ;lbC002FD8 MOVE.W (A0),D1 ; SWAP D1 ; MOVE.W (A0),D1 ; MOVE.B D1,3(A1) ; LSR.L #8,D1 ; MOVE.W D1,1(A1) ; SWAP D1 ; MOVE.B D1,(A1) ; ADDQ.W #4,A1 ; DBRA D0,lbC002FD8 ; BRA.S lbC002FB2 ;lbC002FF4 MOVEA.L $60(A3),A1 ; write data (512 bytes) ; MOVEA.L A4,A0 ; MOVE.L A1,D1 ; BTST #0,D1 ; BNE.S lbC003052 ; MOVEQ #15,D0 ;lbC003004 MOVE.W (A1)+,(A0) ; from even address ; MOVE.W (A1)+,(A0) ; MOVE.W (A1)+,(A0) ; MOVE.W (A1)+,(A0) ; MOVE.W (A1)+,(A0) ; MOVE.W (A1)+,(A0) ; MOVE.W (A1)+,(A0) ; MOVE.W (A1)+,(A0) ; MOVE.W (A1)+,(A0) ; MOVE.W (A1)+,(A0) ; MOVE.W (A1)+,(A0) ; MOVE.W (A1)+,(A0) ; MOVE.W (A1)+,(A0) ; MOVE.W (A1)+,(A0) ; MOVE.W (A1)+,(A0) ; MOVE.W (A1)+,(A0) ; DBRA D0,lbC003004 ;lbC003028 MOVE.L A1,$60(A3) ; MOVEA.L $6C(A3),A0 ; ADDI.L #$200,8(A0) ; ADDQ.B #1,D3 ; CMP.B $6C(A2),D3 ; BCS.S lbC003042 ; MOVEQ #0,D3 ;lbC003042 SUBQ.B #1,$4A(A3) ; BNE.W lbC002F18 ; MOVEQ #0,D3 ; MOVEQ #6,D2 ; 6 input ; BRA.W lbC002F18 ;lbC003052 MOVEQ #$7F,D0 ; from odd address ;lbC003054 MOVE.B (A1),D1 ; SWAP D1 ; MOVE.W 1(A1),D1 ; LSL.L #8,D1 ; MOVE.B 3(A1),D1 ; SWAP D1 ; MOVE.W D1,(A0) ; SWAP D1 ; MOVE.W D1,(A0) ; ADDQ.W #4,A1 ; DBRA D0,lbC003054 ; BRA.S lbC003028 ;lbC003072 MOVEA.L $6C(A3),A0 ; SUBI.L #$200,8(A0) ;lbC00307E BSR.S GetError ; BRA.W lbC002F78 ;GetError BTST #6,$15(A2) ; BEQ.S lbC003092 ; BSR.W lbC00231C ; why ? buggy call for me (wrong output) ; BRA.S lbC0030BE ;lbC003092 MOVE.B $16-Modulo(A4),D0 ; LSL.W #8,D0 ; MOVE.B $12-Modulo(A4),D0 ; MOVE.W $5E(A2),D1 ; MULU.W D0,D1 ; MOVE.L D1,-(SP) ; MOVE.B $1A-Modulo(A4),D0 ; AND.W #15,D0 ; MOVEQ #0,D1 ; MOVE.B $65(A2),D1 ; MULU.W D0,D1 ; ADD.L (SP)+,D1 ; MOVE.B 14-Modulo(A4),D0 ; SUBQ.B #1,D0 ; ADD.L D0,D1 ;lbC0030BE MOVE.L D1,$68(A2) ; MOVEQ #2,D0 ; RTS ;lbC0030C6 MOVEA.L $68(A3),A1 ; MOVE.B D0,(A1) ; RTS ; ReadWriteData (final version - 17 XII 2012) ; input D0 ; output D0 ; changed D0/D1/A0/A1 ; input D0 = 0/2/4 ; 0 = no data ; 2 = read command ; 4 = write command ifne MC68000 OddWrite moveq #$7F,D0 ; from odd address LoopWO move.l 1(A2),D1 ; 2/3/4/x move.b (A2),D1 ; 2/3/4/1 rol.l #8,D1 ; 3/4/1/2 move.w D1,(A4) swap D1 move.w D1,(A4) addq.l #4,A2 dbf D0,LoopWO bra.b BackW endc ReadWriteData movem.l D2/D3/D4/D5/D6/A2,-(SP) move.b $6C(A2),D4 move.l $60(A3),A2 move.b $4A(A3),D6 move.l $20(A5),D5 moveq #0,D2 subq.w #2,D0 beq.b GoR subq.w #2,D0 beq.b GoW bra.b QuitW ; WriteData routine LoopW subq.b #1,D6 beq.b QuitW move.l D5,D0 jsr -$13E(A6) ; Wait GoW moveq #0,D3 WaitForReadyW move.b $1E-Modulo(A4),D0 bmi.b WaitForReadyW lsr.b #1,D0 bcs.b ErrorW lsr.b #3,D0 bcc.b WaitForReadyW ifne MC68000 move.l A2,D1 btst #0,D1 bne.b OddWrite endc moveq #15,D0 LoopWE move.w (A2)+,(A4) ; from even address move.w (A2)+,(A4) move.w (A2)+,(A4) move.w (A2)+,(A4) move.w (A2)+,(A4) move.w (A2)+,(A4) move.w (A2)+,(A4) move.w (A2)+,(A4) move.w (A2)+,(A4) move.w (A2)+,(A4) move.w (A2)+,(A4) move.w (A2)+,(A4) move.w (A2)+,(A4) move.w (A2)+,(A4) move.w (A2)+,(A4) move.w (A2)+,(A4) dbf D0,LoopWE BackW addq.l #1,D2 addq.b #1,D3 cmp.b D4,D3 bcc.b LoopW subq.b #1,D6 bne.b WaitForReadyW QuitW move.l D5,D0 jsr -$13E(A6) ; Wait WaitW move.b $1E-Modulo(A4),D0 bmi.b WaitW bra.b QuitR ErrorW subq.l #1,D2 ErrorR move.l A2,$60(A3) move.l 20(SP),A2 ; restore A2 move.b 6-Modulo(A4),$277(A2) bsr.b GetError bra.b QuitE ; ReadData routine LoopR subq.b #1,D6 beq.b QuitR GoR moveq #0,D3 move.l D5,D0 jsr -$13E(A6) ; Wait WaitForReadyR move.b $1E-Modulo(A4),D0 bmi.b WaitForReadyR lsr.b #1,D0 bcs.b ErrorR lsr.b #3,D0 bcc.b WaitForReadyR ifne MC68000 move.l A2,D1 btst #0,D1 bne.b OddRead endc moveq #15,D0 LoopRE move.w (A4),(A2)+ ; even address copy routine move.w (A4),(A2)+ move.w (A4),(A2)+ move.w (A4),(A2)+ move.w (A4),(A2)+ move.w (A4),(A2)+ move.w (A4),(A2)+ move.w (A4),(A2)+ move.w (A4),(A2)+ move.w (A4),(A2)+ move.w (A4),(A2)+ move.w (A4),(A2)+ move.w (A4),(A2)+ move.w (A4),(A2)+ move.w (A4),(A2)+ move.w (A4),(A2)+ dbf D0,LoopRE BackR addq.l #1,D2 addq.b #1,D3 cmp.b D4,D3 bcc.b LoopR subq.b #1,D6 bne.b WaitForReadyR QuitR move.l A2,$60(A3) moveq #0,D0 ; success QuitE move.l $6C(A3),A0 lsl.l #8,D2 ; *256 add.l D2,D2 ; *512 add.l D2,8(A0) move.b D6,$4A(A3) movem.l (SP)+,D2/D3/D4/D5/D6/A2 rts ifne MC68000 OddRead moveq #$7E,D0 ; odd address copy routine LoopRO move.w (A4),D1 swap D1 move.w (A4),D1 ; 1/2/3/4 rol.l #8,D1 ; 2/3/4/1 move.b D1,(A2)+ move.l D1,(A2) addq.l #3,A2 dbf D0,LoopRO move.w (A4),D1 ; necessary due last byte is overwritten swap D1 move.w (A4),D1 ; 1/2/3/4 rol.l #8,D1 ; 2/3/4/1 move.b D1,(A2)+ move.b 3(A2),D1 ; backup original byte value move.l D1,(A2) addq.l #3,A2 bra.b BackR endc GetError btst #6,$15(A2) beq.b CalcError bsr.w lbC00231C bra.b PutError CalcError move.b $16-Modulo(A4),D1 lsl.w #8,D1 move.b $12-Modulo(A4),D1 mulu.w $5E(A2),D1 moveq #15,D0 and.b $1A-Modulo(A4),D0 moveq #0,D3 move.b $65(A2),D3 mulu.w D0,D3 add.l D3,D1 move.b 14-Modulo(A4),D0 subq.b #1,D0 add.l D1,D0 PutError move.l D0,$68(A2) ; here is my fix D1 replaced with D0 moveq #2,D0 ; error rts |
18 December 2012, 19:47 | #2 |
Paranoid Amigoid
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:O
Awesome!!! Nice to have a new scsi.device mate /kudos. |
19 December 2012, 01:14 | #3 |
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Whoah, this is REALLY nice!!
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20 December 2012, 10:28 | #4 |
The 1 who ribbits
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yay finaly we might get the 1 scsi.device that dos everything, and of course dose it brilantly
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21 December 2012, 09:28 | #5 |
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Next version is available, I optimised a few ReadWriteData routine.
Code:
; ReadWriteData (final version - 20 XII 2012) ; input D0 ; output D0 ; changed D0/D1/A0/A1 ; input D0 = 0/2/4 ; 0 = no data ; 2 = read command ; 4 = write command ifeq MC68000 NoData move.l $20(A5),D0 jsr -$13E(A6) ; Wait WaitND move.b $1E-Modulo(A4),D0 bmi.b WaitND moveq #0,D0 ; no error rts ReadWriteData tst.w D0 ; CCR set beq.b NoData movem.l D2/D4/D5/D6/A5,-(SP) move.l $20(A5),D5 move.b $6C(A2),D4 ; maximum number of blocks per track ? move.l $60(A3),A5 ; destination/source ptr move.b $4A(A3),D6 ; number of blocks to read/write moveq #0,D2 subq.w #4,D0 bne.b GoR bra.b GoW ; ReadData routine LoopR subq.b #1,D1 bne.b WaitForReadyR GoR move.l D5,D0 jsr -$13E(A6) ; Wait move.b D4,D1 WaitForReadyR move.b $1E-Modulo(A4),D0 bmi.b WaitForReadyR lsr.b #1,D0 bcs.b ErrorR lsr.b #3,D0 bcc.b WaitForReadyR moveq #15,D0 LoopRE move.w (A4),(A5)+ ; 68020+ copy routine move.w (A4),(A5)+ move.w (A4),(A5)+ move.w (A4),(A5)+ move.w (A4),(A5)+ move.w (A4),(A5)+ move.w (A4),(A5)+ move.w (A4),(A5)+ move.w (A4),(A5)+ move.w (A4),(A5)+ move.w (A4),(A5)+ move.w (A4),(A5)+ move.w (A4),(A5)+ move.w (A4),(A5)+ move.w (A4),(A5)+ move.w (A4),(A5)+ dbf D0,LoopRE addq.l #8,D2 ; *8 subq.b #1,D6 bne.b LoopR QuitR moveq #0,D0 ; no error QuitE move.l A5,$60(A3) move.l $6C(A3),A0 lsl.l #6,D2 ; *64 add.l D2,8(A0) move.b D6,$4A(A3) movem.l (SP)+,D2/D4/D5/D6/A5 rts ErrorW subq.l #8,D2 ErrorR move.b 6-Modulo(A4),$277(A2) bsr.b GetError bra.b QuitE ; WriteData routine LoopW subq.b #1,D1 bne.b WaitForReadyW move.l D5,D0 jsr -$13E(A6) ; Wait GoW move.b D4,D1 WaitForReadyW move.b $1E-Modulo(A4),D0 bmi.b WaitForReadyW lsr.b #1,D0 bcs.b ErrorW lsr.b #3,D0 bcc.b WaitForReadyW moveq #15,D0 LoopWE move.w (A5)+,(A4) ; 68020+ copy routine move.w (A5)+,(A4) move.w (A5)+,(A4) move.w (A5)+,(A4) move.w (A5)+,(A4) move.w (A5)+,(A4) move.w (A5)+,(A4) move.w (A5)+,(A4) move.w (A5)+,(A4) move.w (A5)+,(A4) move.w (A5)+,(A4) move.w (A5)+,(A4) move.w (A5)+,(A4) move.w (A5)+,(A4) move.w (A5)+,(A4) move.w (A5)+,(A4) dbf D0,LoopWE addq.l #8,D2 ; *8 subq.b #1,D6 bne.b LoopW move.l D5,D0 jsr -$13E(A6) ; Wait WaitW move.b $1E-Modulo(A4),D0 bmi.b WaitW bra.b QuitR GetError btst #6,$15(A2) beq.b CalcError bsr.w lbC00231C bra.b PutError CalcError move.b $16-Modulo(A4),D1 lsl.w #8,D1 move.b $12-Modulo(A4),D1 mulu.w $5E(A2),D1 moveq #15,D0 and.b $1A-Modulo(A4),D0 moveq #0,D4 move.b $65(A2),D4 mulu.w D0,D4 add.l D4,D1 move.b 14-Modulo(A4),D0 subq.b #1,D0 add.l D1,D0 PutError move.l D0,$68(A2) ; here is my fix D1 replaced with D0 moveq #2,D0 ; error rts else NoData move.l $20(A5),D0 jsr -$13E(A6) ; Wait WaitND move.b $1E-Modulo(A4),D0 bmi.b WaitND moveq #0,D0 ; no error rts LoopROB subq.b #1,D3 bne.b WaitForReadyRO GoRO move.l D5,D0 jsr -$13E(A6) ; Wait move.b D4,D3 WaitForReadyRO move.b $1E-Modulo(A4),D0 bmi.b WaitForReadyRO lsr.b #1,D0 bcs.w ErrorR btst #2,D0 beq.b WaitForReadyRO moveq #$7E,D0 ; odd address copy routine LoopRO move.w (A4),D1 swap D1 move.w (A4),D1 ; 1/2/3/4 rol.l #8,D1 ; 2/3/4/1 move.b D1,(A5)+ move.l D1,(A5) addq.l #3,A5 dbf D0,LoopRO move.w (A4),D1 ; necessary due last byte is overwritten swap D1 move.w (A4),D1 ; 1/2/3/4 rol.l #8,D1 ; 2/3/4/1 move.b D1,(A5)+ move.b 3(A5),D1 ; backup original byte value move.l D1,(A5) addq.l #3,A5 addq.l #8,D2 ; *8 subq.b #1,D6 bne.b LoopROB bra.b QuitR OddCopy subq.w #4,D0 bne.b GoRO bra.w GoWO ReadWriteData tst.w D0 ; CCR set beq.b NoData movem.l D2/D3/D4/D5/D6/A5,-(SP) move.l $20(A5),D5 move.b $6C(A2),D4 ; maximum number of Blocks per Track ? move.l $60(A3),A5 ; destination/source ptr move.b $4A(A3),D6 ; number of blocks to read/write moveq #0,D2 move.l A5,D1 lsr.b #1,D1 bcs.b OddCopy subq.w #4,D0 bne.b GoR bra.b GoW ; ReadData routine LoopR subq.b #1,D3 bne.b WaitForReadyR GoR move.l D5,D0 jsr -$13E(A6) ; Wait move.b D4,D3 WaitForReadyR move.b $1E-Modulo(A4),D0 bmi.b WaitForReadyR lsr.b #1,D0 bcs.b ErrorR btst #2,D0 beq.b WaitForReadyR moveq #15,D0 LoopRE move.w (A4),(A5)+ ; even address copy routine move.w (A4),(A5)+ move.w (A4),(A5)+ move.w (A4),(A5)+ move.w (A4),(A5)+ move.w (A4),(A5)+ move.w (A4),(A5)+ move.w (A4),(A5)+ move.w (A4),(A5)+ move.w (A4),(A5)+ move.w (A4),(A5)+ move.w (A4),(A5)+ move.w (A4),(A5)+ move.w (A4),(A5)+ move.w (A4),(A5)+ move.w (A4),(A5)+ dbf D0,LoopRE addq.l #8,D2 ; *8 subq.b #1,D6 bne.b LoopR QuitR moveq #0,D0 ; no error QuitE move.l A5,$60(A3) move.l $6C(A3),A0 lsl.l #6,D2 ; *64 add.l D2,8(A0) move.b D6,$4A(A3) movem.l (SP)+,D2/D3/D4/D5/D6/A5 rts ErrorW subq.l #8,D2 ErrorR move.b 6-Modulo(A4),$277(A2) bsr.b GetError bra.b QuitE ; WriteData routine LoopW subq.b #1,D3 bne.b WaitForReadyW move.l D5,D0 jsr -$13E(A6) ; Wait GoW move.b D4,D3 WaitForReadyW move.b $1E-Modulo(A4),D0 bmi.b WaitForReadyW lsr.b #1,D0 bcs.b ErrorW btst #2,D0 beq.b WaitForReadyW moveq #15,D0 LoopWE move.w (A5)+,(A4) ; from even address move.w (A5)+,(A4) move.w (A5)+,(A4) move.w (A5)+,(A4) move.w (A5)+,(A4) move.w (A5)+,(A4) move.w (A5)+,(A4) move.w (A5)+,(A4) move.w (A5)+,(A4) move.w (A5)+,(A4) move.w (A5)+,(A4) move.w (A5)+,(A4) move.w (A5)+,(A4) move.w (A5)+,(A4) move.w (A5)+,(A4) move.w (A5)+,(A4) dbf D0,LoopWE addq.l #8,D2 ; *8 subq.b #1,D6 bne.b LoopW BackW move.l D5,D0 jsr -$13E(A6) ; Wait WaitW move.b $1E-Modulo(A4),D0 bmi.b WaitW bra.b QuitR GetError btst #6,$15(A2) beq.b CalcError bsr.w lbC00231C bra.b PutError CalcError move.b $16-Modulo(A4),D1 lsl.w #8,D1 move.b $12-Modulo(A4),D1 mulu.w $5E(A2),D1 moveq #15,D0 and.b $1A-Modulo(A4),D0 moveq #0,D3 move.b $65(A2),D3 mulu.w D0,D3 add.l D3,D1 move.b 14-Modulo(A4),D0 subq.b #1,D0 add.l D1,D0 PutError move.l D0,$68(A2) ; here is my fix D1 replaced with D0 moveq #2,D0 ; error rts LoopWOB subq.b #1,D3 bne.b WaitForReadyWO move.l D5,D0 jsr -$13E(A6) ; Wait GoWO move.b D4,D3 WaitForReadyWO move.b $1E-Modulo(A4),D0 bmi.b WaitForReadyWO lsr.b #1,D0 bcs.w ErrorW btst #2,D0 beq.b WaitForReadyWO moveq #$7F,D0 ; from odd address LoopWO move.l 1(A5),D1 ; 2/3/4/x move.b (A5),D1 ; 2/3/4/1 rol.l #8,D1 ; 3/4/1/2 move.w D1,(A4) swap D1 move.w D1,(A4) addq.l #4,A5 dbf D0,LoopWO addq.l #8,D2 ; *8 subq.b #1,D6 bne.b LoopWOB bra.w BackW endc |
24 December 2012, 14:17 | #6 |
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Next version is available. Trashed register for A1200/A4000 versions is fixed (my bug).
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26 December 2012, 11:45 | #7 |
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Tried out incorporating your scsi.device into my custom ROM, but my A1200 refuses to boot then. The ROM gets kicked via ACAtune but then my A1200 freezes.
Can it be due to this patch is missing: SCSI4345p.readme ? My A1200 setup with 4 GB CF-Card and 2 PFS3 partitions only boots with scsidev 43.45 or Cosmos 43.47. |
26 December 2012, 19:22 | #8 | |
MC68060@85MHz
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Quote:
To verify, check if problem exists with scsi.device 43.43 from OS3.9 (or 3.9 BB1, not sure). EDIT: I checked - I use 43.45 so same as yours. But anyway, some versions (ie. the 44.2) refuse to work for me so try some different versions, also try another drive and partition it with new scsidev. I will later try this new scsi from Don_Adan and tell you how it works for me. |
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27 December 2012, 01:02 | #9 |
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Hi Don,
That's some Awesome work you have done on the IDE versions of scsi.device! Do you think you could help improve one of the real versions of scsi.device? http://eab.abime.net/showthread.php?t=67144 |
29 December 2012, 16:03 | #10 |
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Next version is available, one my bug fixed, more routines reworked, can be a few fastest.
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29 December 2012, 16:07 | #11 | |
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Quote:
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29 December 2012, 16:11 | #12 | |
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Quote:
Last edited by Don_Adan; 29 December 2012 at 19:02. |
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29 December 2012, 19:13 | #13 | |
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Quote:
I did upload the complete A2091 16KB binary to the Zone. I've done a raw dis-assembly of this binary but I have a few problems. The disassembler does not seem know the difference between real 68K code and data structures and I don't know enough about AmigaOS code and data structures to separate them yet. But I'll post some more technical info on the A2091 thread and I can test any modified versions myself. |
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31 December 2012, 00:43 | #14 | |
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However at the moment it is a little bit slower than Cosmos v43.47, 2320 KB/s vs. 2530 KB/s on my CF-Card. |
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01 January 2013, 18:15 | #15 | |
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Your binary version is wrong, you splitted both ROM files in wrong rotation. Now you can make fixes/changes inside source. After assembling, you must remove/cut first 32 bytes and last 4 bytes from exe version to receive binary version. Later perhaps you must split binary file on two ROM parts. Remember this ROM file is fully PC relative (except module structure part), then don't use non PC relative code for your changes. |
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01 January 2013, 18:19 | #16 |
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I don't remove/change wait code for now, maybe later it can be changed too. Which speed value occured for v43.45 on your setup?
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01 January 2013, 19:01 | #17 | |
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The version I posted in the Zone was a ROM Ripped version due to lack of any Amiga software I could find to merge the even/odd binary's previously posted here on EAB. A modified and reassembled binary would have to be split into even/odd for ROM programming. PC relative is absolutely required since the A2091 ROMs can be Auto-Configed in any 64KB block of Zorro2 I/O space. Last edited by SpeedGeek; 02 January 2013 at 17:59. |
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01 January 2013, 23:30 | #18 |
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Awesome, can't wait to try this
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03 January 2013, 18:27 | #19 |
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Hi Don,
Here are some hardware design considerations for code optimizing the IDE versions of scsi.device: - 68020/68030 internally handle dynamic bus sizing more efficiently than most 040/060 CPU cards. This is one reason (but not the only one) why word transfers seem to give better performance with 040/060. - The A4000 state machine logic terminates the cycle on the CPU side of the bus approx. 5 clocks before the IDE side of the bus terminates it's cycle. The idea is to free the CPU to perform some other task while waiting for the IDE bus cycle to complete. This is more friendly to the OS in terms of CPU usage but if the CPU commits to a longer bus cycle due to a slower task or accessing a slower port it can delay the start of the next IDE bus cycle (resulting in a slower transfer rate). - The 040/060 have larger internal caches and improved instruction execution pipelines so they are more likely to complete tasks and be ready to begin the next cycle on the IDE bus (but they can still be delayed by accessing a slower external port) and another reason why word transfers may be seem give a better performance with 040/060. As you can see there are performance trade offs with word vs. longword transfers and CPU usage vs. IDE max. transfer rate. I hope this can be of some help to you. Last edited by SpeedGeek; 03 January 2013 at 18:37. |
03 January 2013, 18:44 | #20 |
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My friend/tester reached over 3MB/s on A4000 CS 68060 80MHz, when maximum for PIO-0 is perhaps 3.3 MB/s. I don't know if A4000 IDE controller can works in PIO-2 or PIO-4 mode for reach better speed.
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