New Universal Agnus 8372, 75 etc

[Mathesar]

Originally Posted by nonarkitten

Idle tones? My implementation follows the PDM + PWM and does not sound off at all.

A delta-sigma modulator will generate a constant output pattern when fed with a DC "voltage". This output pattern is heard as an idle tone.
For example, in the case of an 8bit delta-sigma modulator fed with "+1" or 0x01, the carry output will output 1 every 256th clock pulse.
At 3.57MHz clock this will generate a ~14Khz idle tone. If this carry is then fed into another adder to combine 2 channels this idle tone will further be divided down to 7KHz or lower which is definitely audible.
If volume is also applied this tone could be further divided down in frequency. In effect you have 6bits volume + 8bits audio = 14bits of audio resolution. And a single order delta-sigma modulator cannot cleanly reproduce this resolution in the audio band @3.57MHz clock rate. A higher order modulator is needed to achieve that.

I believe you when you say it doesn't sound of. Most of the time it will sound OK but there are edge cases (certain mod files / players) that leave a DC component on the DAC registers which will cause audible noise trails or idle tones.

[pandy71]

Originally Posted by Mathesar

A delta-sigma modulator will generate a constant output pattern when fed with a DC "voltage". This output pattern is heard as an idle tone.
For example, in the case of an 8bit delta-sigma modulator fed with "+1" or 0x01, the carry output will output 1 every 256th clock pulse.
At 3.57MHz clock this will generate a ~14Khz idle tone. If this carry is then fed into another adder to combine 2 channels this idle tone will further be divided down to 7KHz or lower which is definitely audible.
If volume is also applied this tone could be further divided down in frequency. In effect you have 6bits volume + 8bits audio = 14bits of audio resolution. And a single order delta-sigma modulator cannot cleanly reproduce this resolution in the audio band @3.57MHz clock rate. A higher order modulator is needed to achieve that.

I believe you when you say it doesn't sound of. Most of the time it will sound OK but there are edge cases (certain mod files / players) that leave a DC component on the DAC registers which will cause audible noise trails or idle tones.

Idle tones can be suppressed by adding dither signal to samples. Of course to keep noise floor at reasonable level this will require use of bigger sample depth - at least 16..18 bits where 2 lower bits can be sacrificed for dither signal. Idle tones in DSM is way lower issue when multi-bit DSM is used (for example 16 bit DSM that feed for example 4 bit PWM)

I don't understand how possible is to use PWM with PDM - my understanding of electronics lead me to conclusion if 6 bit PWM require clock 64 times (at least) higher than sample rate then based on this is PDM require (single bit, first order, 50dB SNR) at least 64 times oversampling. This means that clock should be at least 4096 times higher than maximum sample rate. Unless PWM control analog value (for example Vref) so it is no longer digital...

Quite obvious is to use multiplier performing volume control by multiplying sample value (8 bit) by 6 bit volume as such producing 14 bit word length (seem this is common method dealing with Amiga audio emulation in SW and HW today)...

[robinsonb5]

Originally Posted by pandy71

(for example 16 bit DSM that feed for example 4 bit PWM)

That's exactly the solution I settled on (though actually for different reasons - I know nonarkitten has seen my blog post on the subject).

I don't understand how possible is to use PWM with PDM

I think the idea is to use the PWM to gate the incoming value into the PDM - so you either add the current sample value or zero to the accumulator, depending on the PWM's output. But yes, it will result in those idle tones dropping yet further in pitch.

Quite obvious is to use multiplier performing volume control by multiplying sample value (8 bit) by 6 bit volume as such producing 14 bit word length (seem this is common method dealing with Amiga audio emulation in SW and HW today)...

The thought process is that if Paula's DACs are analogue (*if*) then a digital recreation can't be perfectly accurate, so if there are multipliers available they might as well be used. I'd be very interested to see some evidence to back up the idea that they're digital - should be easy enough to see on a scope placed on Paula's output pins.

My standard "test suite" when I was tinkering with this stuff was as follows:
* Play "Stardust Memories" in a version of ProTracker with a master volume control, set one step above silence. Record on PC, amplify to normal listening levels, see how recognisable / noisy the result is.
* Play the intro tune from Gauntlet III - the closing arpeggio fades out to nothing, and triggers some strangely modulated idle tones in its dying gasps.
* Play the game "Gods", where the reverb tail on the footstep sounds can trigger some louder-than-expected noise with some DACs.
* Also in "Gods" jumping sometimes causes the audio to be parked on values very close to but not quite zero, which again can result in audible idle tones.

I believe that the symptoms these tests highlighted were at least in part due to FPGA pin switching and reconstruction filter characteristics rather than the DACs under test, per se - so the selfsame tests on different hardware might yield different results.

[pandy71]

Originally Posted by robinsonb5

That's exactly the solution I settled on (though actually for different reasons - I know nonarkitten has seen my blog post on the subject).

Issue with PDM (DSM) is that single bit DSM are inherently unstable and unsuitable for proper DAC.
Alternatively to single bit DSM a multi bit DSM can be used at a cost of all troubles common for multibit architectures.
PWM is neat workaround as it is inherently linear (assumption is sufficient time accuracy but this is critical also for DSM) thus able to deliver multibit without common multibit issues - limitations is of course frequency - for 8 bit PWM a 256 times faster clock than samplerate and for 16 bit 65536 times faster clock.

But putting together PDM (DSM) and PWM can create nice couple - you can use multibit, high order DSM and keep frequency and linearity within sane limits.

Originally Posted by robinsonb5

I think the idea is to use the PWM to gate the incoming value into the PDM - so you either add the current sample value or zero to the accumulator, depending on the PWM's output. But yes, it will result in those idle tones dropping yet further in pitch.

This will not work - unless you going to 4096 times sample rate. Such approach is unable to mimic Paula audio path where sample rate is 3.58MHz

Originally Posted by robinsonb5

The thought process is that if Paula's DACs are analogue (*if*) then a digital recreation can't be perfectly accurate, so if there are multipliers available they might as well be used. I'd be very interested to see some evidence to back up the idea that they're digital - should be easy enough to see on a scope placed on Paula's output pins.

Well... this is question if Paula replacement should emulate Paula imperfection - IMHO not.

Having perfect 14 bits (6*8 multiplication) is OK for me and remove necessity of calibration.

Originally Posted by robinsonb5

My standard "test suite" when I was tinkering with this stuff was as follows:
* Play "Stardust Memories" in a version of ProTracker with a master volume control, set one step above silence. Record on PC, amplify to normal listening levels, see how recognisable / noisy the result is.
* Play the intro tune from Gauntlet III - the closing arpeggio fades out to nothing, and triggers some strangely modulated idle tones in its dying gasps.
* Play the game "Gods", where the reverb tail on the footstep sounds can trigger some louder-than-expected noise with some DACs.
* Also in "Gods" jumping sometimes causes the audio to be parked on values very close to but not quite zero, which again can result in audible idle tones.

I believe that the symptoms these tests highlighted were at least in part due to FPGA pin switching and reconstruction filter characteristics rather than the DACs under test, per se - so the selfsame tests on different hardware might yield different results.

If i can imagine correctly your description there is lot symptoms for limited quantization (quantization noise) and plenty of aliasing.

To use concept of PWM*PDM without 4096 clock, PWM may control voltage reference for DSM but before being feed to PDM (DSM) it need to be filtered to remove PWM so in other words it must be continuous, analog voltage. But this will create incompatible Paula replacement pinout (need to output separately PWM to be analog filtered externally then can be used to supply DSM).
In Paula this is easier as sample value can be feed to buffer before DAC where buffer is controlled by PWM (or multiplexer switching between 0 and sample value). If DAC is sufficiently high speed (3.58MHz at least) then it is not important from his perspective if sample value occurs 1/64 sample time or 63/64 sample time.

[Gorf]

Originally Posted by robinsonb5

I think the idea is to use the PWM to gate the incoming value into the PDM

That is correct.
The sample is "switched off" up to 64 times during one period, resulting in 64 volume levels.

[pandy71]

Originally Posted by Gorf

That is correct.
The sample is "switched off" up to 64 times during one period, resulting in 64 volume levels.

This means that PWM clock must be 64 times faster than PDM clock.

[Gorf]

This means that PWM clock must be 64 times faster than PDM clock.

no - these are two independent measures applied at different stages.

See also following discussions:

http://eab.abime.net/showthread.php?t=105744
"14.57731 bit audio"

and
http://eab.abime.net/showthread.php?t=105355
"Amiga '14-bit audio' refuted"

[nonarkitten]

Originally Posted by Mathesar

A delta-sigma modulator will generate a constant output pattern when fed with a DC "voltage". This output pattern is heard as an idle tone.
For example, in the case of an 8bit delta-sigma modulator fed with "+1" or 0x01, the carry output will output 1 every 256th clock pulse.

Correct.

Originally Posted by Mathesar

At 3.57MHz clock this will generate a ~14Khz idle tone.

With 1/127th the energy. That should correspond to about a -42dB drop. But I'll comment more on this at the end.

Originally Posted by Mathesar

If this carry is then fed into another adder to combine 2 channels this idle tone will further be divided down to 7KHz or lower which is definitely audible.

The second adder does not cut the frequency in half.

Originally Posted by Mathesar

If volume is also applied this tone could be further divided down in frequency.

But the interplay with PWM and PDM does not work like this. In those 256 PDM cycles we'd have four full PWM cycles. A 1/256th output would not get zeroed out using this scheme until volume is set to zero.

Originally Posted by Mathesar

In effect you have 6bits volume + 8bits audio = 14bits of audio resolution.

If you think about it, it can't be 14-bits of resolution. Simple example take two volumes at 1 and 2, n * 1 versus n * 2. At n * 2, half of levels exactly coincide with the outputs of n * 1, so it doesn't add 256 new levels, it only adds 128. At n * 3, all the levels 0 thru 85 (255) are duplicates from n * 1 and half the levels from 86 to 170 are duplicates from n * 2. So we've already lost a whole bit of resolution, and this is "ideal."

Then, if we're talking effective number of bits, the Amiga really only gets about 10-11 bits. The whole 14-bit audio is a BIT of an exaggeration. But the whole 14-bit thing could be it's own essay..

Originally Posted by Mathesar

And a single order delta-sigma modulator cannot cleanly reproduce this resolution in the audio band @3.57MHz clock rate. A higher order modulator is needed to achieve that.

MiniMig had an incredibly primitive filter compared to any real Amiga, but 14kHz is perfectly filterable even with an RC filter. Most Amiga's cut-off around 4-5kHz. All of this being said, all we would have to do to solve all your gripes is do something like this:

assign CLK7M = CCK ^ ~CCKQ;

I know Gary does this to reconstruct higher clocks. This pushes the lowest frequency to 28kHz which is well above human hearing. I checked, a circa 1984 SN7483 could do a 7MHz add (has a 24ns delay for adding 8-bit values). We also know Commodore was a big fan of multiphase clocks, etc.

Originally Posted by Mathesar

I believe you when you say it doesn't sound of. Most of the time it will sound OK but there are edge cases (certain mod files / players) that leave a DC component on the DAC registers which will cause audible noise trails or idle tones.

There's a problem with comparing how it sounded on MiniMig versus an Amiga.
[ Show youtube player ]

For anyone who hasn't seen it, you should check out this video showing the volume PWM in action. At around 50% the PWM is almost a perfect sawtooth -- there is no flatness. Even near the 0 and 100% it's extremely round and this is with the filters turned off. And this is a 55kHz signal. Yes, with the filters "off" there's still some filtering, but if we've already lost half the signal at 55kHz, nothing should survive at 3.5MHz. It's not the 14kHz that matters here, its the 140ns wide pulse.

This reminds me of to our old S08 driving a 22.5kHz PWM where about 97% to 100% were indistinguishable with even the best oscilloscope.

Now all this speculation aside, we have a lot of evidence. Let's first look at the evidence AGAINST it being a "true" Analog DAC:
- True 8-bit DACs were expensive back in the day
- An 8-bit R2R ladder has non-linearity that's not observed on Amiga
- Paula has been decapped; there are no resistors evident -- there is one solder pad for left and one solder pad for right
- There is also no evidence for a package-in-package solution with a real 8-bit DAC; and it should be added that SoC and PiP was not a thing in 1984
- There are serpentine traces, but this was not a practice at this time to create resistors, nor effective at this process size (this would be a few ohms at best); resistors then were other FETs
- The effective resistance of FETs and serpentine traces is too variable to construct an effective DAC; most chips pull-ups are anywhere between about 10K and 100K
- More common back then would have been 8-pins per L/R and the resistors would have been external; since packages were more expensive than silicon, this would make no sense
- Bax comments about the 3.58MHz speed of the DAC being evident in the FFT's in http://bax.comlab.uni-rostock.de/dl/...mTheoretic.pdf
- Antti stating, "Paula does no interpolation of any kind. Paula's output is strictly a pulse wave, produced on 3546895 Hz frequency, which is the Paula clock rate for PAL systems."
https://bel.fi/alankila/modguide/interpolate.txt
- Most literature uses the term PCM a lot which would not describe a true analog DAC nor the volume PWM
https://en.wikipedia.org/wiki/Original_Chip_Set#Audio
- The OpAmps from Paula are constructed in a Del-Sig configuration. Something MiniMig completely ignored and just did a basic two-order RC filter; short of schematics or scope traces, this is as close to a "smoking gun" as I can see
- The Amiga HRM talks about being able to emit a 1.79MHz square wave if you disable the filters

Arugments for?
- A naive 8-bit PDM & 6-bit PWM does NOT result in "more bits"

With all this aside could you still see apparent analog levels on Paula directly even if it is "PCM"? Sure, because of the bypass on the OpAmp, the source signal is contaminated. To see the "pure" output from Paula on the 500, break JP10A (waaaaaay over on the right side of the board) and sample right off that pad. Disable DMA, set the sample rate to get a 1.79MHz square wave and try setting the values to different.

Then we'll know for sure.

On that last point and some above, I think I'll make some tweaks to the design to remedy this. Regardless of how Paula was architected, I do not have the ability to make a true DAC at all.

[pandy71]

Originally Posted by Gorf

no - these are two independent measures applied at different stages.

life is not so simple - you need 64 times faster clock as chopping constant over time so you need 64 time slots, it could work if you use lowpass filter to remove digital modulation to restore continuous time, in such case you can chop in parallel (within filter settle time).

Originally Posted by Gorf

See also following discussions:

http://eab.abime.net/showthread.php?t=105744
"14.57731 bit audio"

and
http://eab.abime.net/showthread.php?t=105355
"Amiga '14-bit audio' refuted"

i saw this discussions (and partially participated in), but overall you can't ignore math and design limit - there is plenty convolution from physical design limitation there - using pure math in 6*8 multiplication remove all this problems.
We don't know (not aware of Paula schematic similar to Agnus and seem decapping then layout conversion is not done) physical Paula implementation for PWM and DAC as PWM control can be implemented in many ways and will work in Paula same/similarly.
Issue with Paula is that internally it is hybrid system using digital and anlog circuitry where FPGA use plain digital and trying to mimic some analog with digital blocks - this is possible but you need decent DSP (large and expensive FPGA).

[Gorf]

Originally Posted by pandy71

life is not so simple

Life is not ... but Paula might be.
I don't think Glenn Keller cared to much about the reconstruction theory but made it somehow work with what he got ...
He had no clue about chip design - after all Paula was his first!

https://amitopia.com/glennkeller-paula-interview/

[nonarkitten]

Originally Posted by pandy71

life is not so simple - you need 64 times faster clock as chopping constant over time so you need 64 time slots, it could work if you use lowpass filter to remove digital modulation to restore continuous time, in such case you can chop in parallel (within filter settle time).

I'm not sure why you think this 64-fold clock increase is a requirement.

What we definitely DO know is that there's no way in hell Paula had an 8 * 6 bit multiplier on there. That's very clear.

And like it or not, that 55kHz PWM noise is part of Amiga's sound; it gives it character that a PC doesn't have. Don't like it, get a PC.

[Mathesar]

Correct.


With 1/127th the energy. That should correspond to about a -42dB drop. But I'll comment more on this at the end.


The second adder does not cut the frequency in half.


But the interplay with PWM and PDM does not work like this. In those 256 PDM cycles we'd have four full PWM cycles. A 1/256th output would not get zeroed out using this scheme until volume is set to zero.

Hmm, Now that I read your post back I think I know what you mean. You are using an OR port to mix the carry-out's together? Yes, then it't wont divide down further but you also won't get perfect addition of the two channels too. Suppose both channel's PDM streams are exactly in sync, playing the same samples, will you get twice the amplitude ie 6dB more output as opposed to only channel being active?

If you think about it, it can't be 14-bits of resolution. Simple example take two volumes at 1 and 2, n * 1 versus n * 2. At n * 2, half of levels exactly coincide with the outputs of n * 1, so it doesn't add 256 new levels, it only adds 128. At n * 3, all the levels 0 thru 85 (255) are duplicates from n * 1 and half the levels from 86 to 170 are duplicates from n * 2. So we've already lost a whole bit of resolution, and this is "ideal."

When you view it like this then yes again, strictly speaking there are no 2^14 levels being used at a fixed volume level. But the total dynamic range is still 2^14 bits. You can play a 1bit sample at volume 1 and a 8bit sample at volume 64 that's a total range of 14bits.

- True 8-bit DACs were expensive back in the day

I don't know. SID chip has a DDS feeding a real DAC. and that predates Paula. I think mixed signal chips like this were quite common in the days.

- An 8-bit R2R ladder has non-linearity that's not observed on Amiga

It's more likely to be a current-switching DAC.
-

Paula has been decapped; there are no resistors evident -- there is one solder pad for left and one solder pad for right

Which would support the theory of a current-switching DAC.

- There is also no evidence for a package-in-package solution with a real 8-bit DAC; and it should be added that SoC and PiP was not a thing in 1984
- There are serpentine traces, but this was not a practice at this time to create resistors, nor effective at this process size (this would be a few ohms at best); resistors then were other FETs
- The effective resistance of FETs and serpentine traces is too variable to construct an effective DAC; most chips pull-ups are anywhere between about 10K and 100K
- More common back then would have been 8-pins per L/R and the resistors would have been external; since packages were more expensive than silicon, this would make no sense

All because it is probably a current switching DAC.

- Bax comments about the 3.58MHz speed of the DAC being evident in the FFT's in http://bax.comlab.uni-rostock.de/dl/...mTheoretic.pdf

I too think the DAC runs at 3.58MHz in the sense that the DAC registers can be updated at any edge of the 3.58MHz clock. Most of the time the value wouldn't change though.

- Antti stating, "Paula does no interpolation of any kind. Paula's output is strictly a pulse wave, produced on 3546895 Hz frequency, which is the Paula clock rate for PAL systems."
https://bel.fi/alankila/modguide/interpolate.txt
- Most literature uses the term PCM a lot which would not describe a true analog DAC nor the volume PWM
https://en.wikipedia.org/wiki/Original_Chip_Set#Audio

I also think the signal is not interpolated before being fed to the DAC's. It's just a 0th order sample and hold reconstruction affair.
-

The OpAmps from Paula are constructed in a Del-Sig configuration. Something MiniMig completely ignored and just did a basic two-order RC filter; short of schematics or scope traces, this is as close to a "smoking gun" as I can see

Paula has a current output, Minimig has a voltage output and thus a different filter. The first opamp in a real Amiga is a transimpedance amplifier (current to voltage), the second a sallen--key lowpass filter.

- The Amiga HRM talks about being able to emit a 1.79MHz square wave if you disable the filters

Never knew that! Will look it up.

[nonarkitten]

Originally Posted by robinsonb5

That's exactly the solution I settled on (though actually for different reasons - I know nonarkitten has seen my blog post on the subject).

I don't know what you're talking about, I've never been on that website or commented on things like Temporal dithering.

[pandy71]

Originally Posted by Gorf

Life is not ... but Paula might be.
I don't think Glenn Keller cared to much about the reconstruction theory but made it somehow work with what he got ...
He had no clue about chip design - after all Paula was his first!

https://amitopia.com/glennkeller-paula-interview/

CBM designed SID (6581) around DAC (3 of them AFAIR 12 bit each + other DAC's and ADC's on board) so definitely CBM use real DAC in their IC design (this means they had in their layout library already existing and silicone proven DAC).
In those times 8 bit DAC was cheap - DAC08 cost probably around 1$ so at protoboard stage ( https://uber-leet.com/HistoryOfTheAmiga/ ) using 4 DAC's such as DAC08 ( https://www.richis-lab.de/DAC11.htm ) was quite simple and straightforward.

Also when i observe silicone 8364 die pictures obviously there is repeated pattern of 4 identical blocks and this occupy large part of the 8364 die itself.

https://siliconpr0n.org/map/csg/8364r4/mz_mit20x/

Real DAC's in IC's usually not use resistors but instead current sources/mirrors made from scaled (binary weighted) transistors (generally where is possible transistors are used in IC's to replace resistors) and such structures are visible on pictures - there are 4 regular, identical blocks where at each of them (first start at -52nm, -712nm end 3.228u, -120nm , then there are 3 copies bellow) "analog" structure is visible with variable area transistors (IMHO - of course i can be wrong but seem this is obvious, also some bits seem to be same - this could explain some lower linearity) - however strangely there is only 7 distinct "bits" there so or the Paula DAC is only 7 bit or LSB is so small that it use different approach (it may be not different than other transistors).

Internal DAC topology/architecture can be very different - depends on DAC purpose.

All above is based on limited resources available and my intention is not to disrespect anyone so if someone will feel offended please accept my apologies.

[Mathesar]

Originally Posted by pandy71

Real DAC's in IC's usually not use resistors but instead current sources/mirrors made from scaled (binary weighted) transistors (generally where is possible transistors are used in IC's to replace resistors) and such structures are visible on pictures - there are 4 regular, identical blocks where at each of them (first start at -52nm, -712nm end 3.228u, -120nm , then there are 3 copies bellow) "analog" structure is visible with variable area transistors (IMHO - of course i can be wrong but seem this is obvious, also some bits seem to be same - this could explain some lower linearity) - however strangely there is only 7 distinct "bits" there so or the Paula DAC is only 7 bit or LSB is so small that it use different approach (it may be not different than other transistors).

Bruce did some measurements here: https://eab.abime.net/showpost.php?p...&postcount=211
Paula can source or sink current depending on the sign of the input signal. So, then Paula would only need 7bits plus a current mirror for the sign.

[pandy71]

Originally Posted by nonarkitten

I'm not sure why you think this 64-fold clock increase is a requirement.

What we definitely DO know is that there's no way in hell Paula had an 8 * 6 bit multiplier on there. That's very clear.

And like it or not, that 55kHz PWM noise is part of Amiga's sound; it gives it character that a PC doesn't have. Don't like it, get a PC.

Because it is mandatory and real Paula doesn't need PDM as it use real DAC so PWM can control easily DAC if DAC is able to produce 1.76/3.58MHz sample rate. PDM require time for sample and PWM require time for sample. Going in such way you can combine two 8bit PWM to claim 16 bit resolution but this will be not true unless one of them will be clocked 256 times faster than second one so later it can be combined in digital way - Amiga has DAC that provide variable analog signal that can be controlled by PWM so multiplication is made in hybrid analog+digital way.


And PC has nothing about in this case as PWM can be disabled in Amiga (there is 65 states - PWM activity is controlled by bit 6 http://amiga-dev.wikidot.com/hardware:audxvol) .

[pandy71]

Originally Posted by Mathesar

Bruce did some measurements here: https://eab.abime.net/showpost.php?p...&postcount=211
Paula can source or sink current depending on the sign of the input signal. So, then Paula would only need 7bits plus a current mirror for the sign.

So sign inversion can be done in OPAMP in analog domain - 7 bit DAC + sign control.

[nonarkitten]

Originally Posted by pandy71

Because it is mandatory and real Paula doesn't need PDM as it use real DAC so PWM can control easily DAC if DAC is able to produce 1.76/3.58MHz sample rate. PDM require time for sample and PWM require time for sample. Going in such way you can combine two 8bit PWM to claim 16 bit resolution but this will be not true unless one of them will be clocked 256 times faster than second one so later it can be combined in digital way - Amiga has DAC that provide variable analog signal that can be controlled by PWM so multiplication is made in hybrid analog+digital way.


And PC has nothing about in this case as PWM can be disabled in Amiga (there is 65 states - PWM activity is controlled by bit 6 http://amiga-dev.wikidot.com/hardware:audxvol) .

Who's claiming 16-bit resolution. Honestly, I'm starting to question if the Amiga really has 8-bit. Thanks Thomas.

[Mathesar]

Thinking about it, as you cannot support a full external DAC you could gain a few bits by having each channel drive a pin using 3 levels: 1,0 and tristate. A resistor would convert this into a simple current DAC with 3 levels. Four pins in total on the fpga going to 2 pins on Harmony by tying the resistors together. As you now have 3 levels to play with (that's a 1,5bit "DAC") you can make better modulation schemes to avoid idle tones and other problems. For example, you can have one bit less in the modulator. The modulator then controls the tristate enable input of the FPGA output buffer and the sign of the sample the output value of the buffer. One bit less in the modulator pushes your idle tones one octave higher up the band. Tying the resistors together also results in perfect addition of the output channels by the transimpedance amplifier.

[nonarkitten]

Originally Posted by Mathesar

Thinking about it, as you cannot support a full external DAC you could gain a few bits by having each channel drive a pin using 3 levels: 1,0 and tristate. A resistor would convert this into a simple current DAC with 3 levels. Four pins in total on the fpga going to 2 pins on Harmony by tying the resistors together. As you now have 3 levels to play with (that's a 1,5bit "DAC" you can make better modulation schemes to avoid idle tones and other problems. For example, you can have one bit less in the modulator. The modulator then controls the tristate enable input of the FPGA output buffer and the sign of the sample the output value of the buffer. One bit less in the modulator pushes your idle tones one octave higher up the band. Tying the resistors together also results in perfect addition of the output channels by the transimpedance amplifier.

OMG I was just thinking of this.

So I'll conceded that Paula has a current DAC; 7-bits by the looks of it, that source or sink based on the sign. Which is neat. The PWM then "chops" that.

So you're right, to drive this right we need a signal that can PDM between high and high-z for + signals and low and high-z for negative signals. That's pretty easy -- something like:

if (sample[7]) out <= bitstream ? 1'b0 : 1'bz;
else out <= bitstream ? 1'b1 : 1'bz;