Memory Data Structures

Zetr0 · 30 September 2007, 01:33

Hello there forum chummies

I am currently redeveloping an A500 Fast Memory Upgrade fo use with an A600

to make this happen, I am changing the 8 1MB Banks of 30pin simm memory for 1 Bank of 72pin memory

some tech specs

30pin memory

12 Address Lines (0-11)
8 Data Lines (0-1)
1 CAS (Column Address Strobe)
1 RAS (Row Address Strobe)

72pin memory

12 Address Lines (0-11)
32 Data Lines (0-31)
4 CAS (Column Address Strobe)'s
4 RAS (Row Address Strobe)'s
4 PRD (PRD1 - PRD4) (what is this I cannot remember)

Well heres my quandary, in restructuring the memory data I am at a well confusion...

my initial idea was to use the full data lines from D0 to D31 using CAS#0 and RAS#0 thus allowing my to 4 times as much data for each CAS/RAS level (since i am limmited on physical logica space *and 5v power*) I figured i could use CAS0/RAS0 for the first 4MB and then CAS1/RAS1 for the last 4MB (ie bank 2) for a total of 8MB

now the problem I have with that is the initial design (which is known to work) only has 50 DATA lines insted of an expected 64.

so i wonder where (a) I have borked it? and (b) am i attempting to use the 72pin simm data structure in the wrong way...

I could use some help guys

Zetr0 · 30 September 2007, 03:17

Okay, I now have the full 64 addressing lines that i need (total 8MB ram)

the question is, can i still use the accessing method i described above?

DrF · 30 September 2007, 11:56

Many moons ago, I'm thinking late 386, early 486 era there was some kind of 30pin to 72pin SIMM convertors would one of those things not help you somehow?

http://www.berklix.com/scanjet/pics/ram_adapt.jpg

Mind you, looking at it, it seems a purely physical conncetion thingy.

Zetr0 · 30 September 2007, 14:24

@DrF

thats what i was thinking, indeed it just changes the data address / CAS 'n RAS lines!!!

whoot thanks buddy!!!!

DrF · 30 September 2007, 14:34

So could you just get 1 of them and plug it in and thats it done?

Zetr0 · 30 September 2007, 15:17

@DrF

yes and no LOL

depending on the 72pin PORT I am *assuming* that the 30pin simms require to be all the same size and 1mb or higher (imagining that 4-8MB would be thier limmit anyway)

DrF · 30 September 2007, 15:39

Only 1 true way to know :P

Jope · 30 September 2007, 17:38

I remember those.. the different letters mean that they are a different height and point different ways so you could get four into adjacent 72pin slots. :-)

You must use the same size 30pin simms to populate one of those and naturally all four must be present.

30 September 2007, 01:33	#1
Zetr0 Ya' like it Retr0? Join Date: Jul 2005 Location: United Kingdom Age: 49 Posts: 9,768	Memory Data Structures Hello there forum chummies I am currently redeveloping an A500 Fast Memory Upgrade fo use with an A600 to make this happen, I am changing the 8 1MB Banks of 30pin simm memory for 1 Bank of 72pin memory some tech specs 30pin memory 12 Address Lines (0-11) 8 Data Lines (0-1) 1 CAS (Column Address Strobe) 1 RAS (Row Address Strobe) 72pin memory 12 Address Lines (0-11) 32 Data Lines (0-31) 4 CAS (Column Address Strobe)'s 4 RAS (Row Address Strobe)'s 4 PRD (PRD1 - PRD4) (what is this I cannot remember) Well heres my quandary, in restructuring the memory data I am at a well confusion... my initial idea was to use the full data lines from D0 to D31 using CAS#0 and RAS#0 thus allowing my to 4 times as much data for each CAS/RAS level (since i am limmited on physical logica space and 5v power) I figured i could use CAS0/RAS0 for the first 4MB and then CAS1/RAS1 for the last 4MB (ie bank 2) for a total of 8MB now the problem I have with that is the initial design (which is known to work) only has 50 DATA lines insted of an expected 64. so i wonder where (a) I have borked it? and (b) am i attempting to use the 72pin simm data structure in the wrong way... I could use some help guys

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30 September 2007, 03:17	#2
Zetr0 Ya' like it Retr0? Join Date: Jul 2005 Location: United Kingdom Age: 49 Posts: 9,768	Okay, I now have the full 64 addressing lines that i need (total 8MB ram) the question is, can i still use the accessing method i described above?

30 September 2007, 11:56	#3
DrF Blessed A1200 Of TeH Rat Join Date: Aug 2007 Location: Bham, UK Age: 42 Posts: 496	Many moons ago, I'm thinking late 386, early 486 era there was some kind of 30pin to 72pin SIMM convertors would one of those things not help you somehow? http://www.berklix.com/scanjet/pics/ram_adapt.jpg Mind you, looking at it, it seems a purely physical conncetion thingy.

30 September 2007, 14:24	#4
Zetr0 Ya' like it Retr0? Join Date: Jul 2005 Location: United Kingdom Age: 49 Posts: 9,768	@DrF thats what i was thinking, indeed it just changes the data address / CAS 'n RAS lines!!! whoot thanks buddy!!!!

30 September 2007, 14:34	#5
DrF Blessed A1200 Of TeH Rat Join Date: Aug 2007 Location: Bham, UK Age: 42 Posts: 496	So could you just get 1 of them and plug it in and thats it done?

30 September 2007, 15:17	#6
Zetr0 Ya' like it Retr0? Join Date: Jul 2005 Location: United Kingdom Age: 49 Posts: 9,768	@DrF yes and no LOL depending on the 72pin PORT I am assuming that the 30pin simms require to be all the same size and 1mb or higher (imagining that 4-8MB would be thier limmit anyway)

30 September 2007, 15:39	#7
DrF Blessed A1200 Of TeH Rat Join Date: Aug 2007 Location: Bham, UK Age: 42 Posts: 496	Only 1 true way to know :P

30 September 2007, 17:38	#8
Jope - Join Date: Jul 2003 Location: Helsinki / Finland Age: 43 Posts: 9,861	I remember those.. the different letters mean that they are a different height and point different ways so you could get four into adjacent 72pin slots. :-) You must use the same size 30pin simms to populate one of those and naturally all four must be present.

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