Creating a new 020 accel board for A600 (eventually to A500 too)

[Zetr0]

Okay i will break down later what each circuit does with its timings, but to begin i shall just post the raw schematics, I will add some (trivial) dialog later

So this is the PALS and GLUE, it sets up the fundements of the project by providing the signals needed to run an 020, SIZE / DSACK signals to name just a few

[Zetr0]

Hello again

Here we have the configuration of the 020 with an FPU with its appropriate ties, the Lucas uses a PGA version of the 020, so there may be extra / lesser signals required for the TQPF EC version.

the 96PIN DIN interface will provide the basis of for the next phase which is to add Fast Ram to the device.

[Zetr0]

Other features I would like to add would be SCSI, and a couple of Clock ports... maybe even some fast flash memory for ROMS that would be awesome!

[TheCorfiot]

Zetro,,, Awesome mate.....

Would IDE be easier than SCSi, I know the CPU overhead would be higher but, no need for firmware, can use KS2.05 or KS3.1 and IDE Peripherals including CF adapters are cheap and easily available.

I like this project

Thanks for your hard work

[coze]

clockports ! that's a very good idea. how is the clockport implemented exactly ? The A500 68000 CPU slot clockport looked very simple, maybe only a couple of 74X logic chips ? so it's mostly software driven ?

[Zetr0]

@Coze

Ian "Stedy" Steadman has a great circuit for implementation of 2 clock ports in the same memory addressing area as that of the a1200.

check out this site http://www.ianstedman.co.uk/Downloads/downloads.html

With a big thanks to Stedy

heres an overview of clock ports

Heres a description of the signals that make up the clock port

and how to build clock port action (added schematic attached )

[Hungry Horace]

i dont yet have an a600, but its on my list of 'must have for mods'!

i'd certainly be interested in a full 020 version... what would the ram limits be on that? 16 fast? 32?

saying that, 8 meg would prob. suffice for my ECS whdload needs

look forward to seeing the progress on this

[Zetr0]

@HH

the initial prototype will be limited to 8MB, its most likely we will run this out as an up grade as an 020 with 8mb is ample for 99.5% of WHDLoad yummyness! (and 15% of that you cannot use due to aga! lol)

The 8mb is achieved using simple logic and all of the spare addressing space for the 020, but by kinda paging memory into and out of a window of this you can have any size you want even Gigabytes LOL.

however it essentially it comes down to the complexity of the memory handler / controller.. the more complex it is the more memory (matrices and types) it can handle (and hence cost), but a safe bet will be the common 32mb 72pin simm type, and this will be max for the 030 version. again depending on complexity may run 2 or more ports for 64mb or greater.

but we shall see...

[Hungry Horace]

i just like 16 meg for "safety" with whdload, but i see where you are coming from Zetr0 for sure an 020 is fine for an a600.

definately have some 8mb (john) simms spare anyway

now where's that s-videtr0 adaptor?

[cv643d]

Im Amazed Alexh has not expressed his optimistic views on this project yet :-)

[Zetr0]

Originally Posted by cv643d

Im Amazed Alexh has not expressed his optimistic views on this project yet :-)

I believe our beloved Alexh knows that its more a matter of time than difficulty as all that needs to be done, has been done its just integrating them all together



....and besides i am sure he is waiting for page 2 to make an opinion.

[Stedy]

@Zetro,

I just realised, I have not updated the A500 clockport design webpage with the final schematics. The DTACK assertion logic is missing.

For various reasons I stopped all classic Amiga development work back in 2006 and never got around to updating that webpage.

@Thread.

The 68881 FPU is obsolete but the 68882 is available, so it is worth updating the design to use the later.

Consider using a Xilinx Coolrunner or Altera MAX II CPLD for the glue logic. These parts cost £1-10 and will easily do the function of the PALs/GALs of the Lucas design.

The Xilinx XC9572-7-PC44 CPLD was the device I targeted when I wrote some VHDL to interface a Coldfire to the Amiga (design was never used). This is a 72 macrocell part available in a 44 pin PLCC package for $7.50 from Digikey and other suppliers.

There are designs on the web for download/programming cables for both Altera and Xilinx parts that connect to the parallel port, couple this with free development software and have some fun!

I found this little list to convert the ABEL equations of Lucas to VHDL/Verilog

ABEL Symbol Description
# OR gate,
.D D-type flip flop/latched input.
& AND gate,
= Combinatorial statement/assignment
! NOT gate/invert

I hope this inspires you to continue.

Ian

[rkauer]

@All: I'm reading the Amiga TECHNICAL manual, also 020 and 030 data sheets, and before someone have funny ideas:

Clockports are OK, like Zetr0 mentioned. But since an EC020 can handle 24 bits of data, the memory limit is 48Mb, included the ROM area, autoconfig space (PCMCIA, clock port) and RAM. So only 32+8Mb without bank swap (who is slow, anyway). If we squeeze the address range, more 1.5Mb "SLOW" RAM =41.5Mb FAST, but with two 32Mb SIMM (or one 32 and one 16Mb). But since the slow RAM is in the FAST controller, no wait states. Formerly 41.5 FAST.

But I think this 1.5Mb is useless and only put more complexity in the design.

8Mb in an A600 is almost an overkill. Remember: BILL GAY said "640kb of memory is enough to anyone!"

Note just one thing: we planning 3 versions of the board: EC020 (up to 28MHz, if the perfoboard prototype runs fine), "full" 020 and 030 (theoretical 4Tb of memory), but we think in a more humble goal: 128Mb in two 72 pin SIMM, due space limitation), thanks to the 32bits address space (all out the 16Mb window space, full autoconfig).

Maybe EDO or a modern memory slot, like ZIP, for example, NOOOOO!, I mean a DIMM slot, but this is controversial (even between me and Z). Expect a more expensive card, of course. The sky is the limit!

The SCSI controller, IDE controller (for the 500/2k version) will become in a add-on slot, for the future versions (if they exists)...

[Zetr0]

@Stedy

thanks for the extra inspiration and you advice (I am sure we will need it )), well i certainly will *as you know lol* )

I about to send out two dev kits, one to RKauer and one to TheCorfiot

amongst many things, it includes

• 3* Xilinx XCR3 128XL - 10c SMD (3.3volt 5 volt signal tolerant)
• 4* SMD 3.3volt regulators
• 3* Xilinx XC7336 36 macro cell 5 volt
• 4* 5 volt regulators
• 2* 68EC020FG25

It would be really Awesome to be able implement the "Stedy Clock" circuit

[coze]

Originally Posted by rkauer

But since an EC020 can handle 24 bits of data, the memory limit is 48Mb, included the ROM area, autoconfig space (PCMCIA, clock port) and RAM.

you mean 24 bit address bus right ? so I think it makes 16 mb not 48 mb and this is exactly the same situation with all 68000 based amigas and the A1200 (which has EC020). 8mb is reserved for custom chips & chip ram and stuff and you get 8mb for fast ram / zorro 2 space. 4 mb if you use pcmcia.

anyway this project will be great even with only 8mb ram, so please go for it !

[rkauer]

Originally Posted by coze

you mean 24 bit address bus right ? so I think it makes 16 mb not 48 mb and this is exactly the same situation with all 68000 based amigas and the A1200 (which has EC020). 8mb is reserved for custom chips & chip ram and stuff and you get 8mb for fast ram / zorro 2 space. 4 mb if you use pcmcia.

anyway this project will be great even with only 8mb ram, so please go for it !

My mistake again. I made the same error very often.

Strange for a tech guy...

[Zetr0]

@rkauer

i find i make them all the time.... i blame my OCD... everyone whoms anyone has one

but do i really make them.... or DO i subtly place errors for people to discover eh?


yeah.... your right.... i make 'em..... I made a completely retarded a while back that only got discovered earlier,

I followed some badly drawn schematics that i was given from aminet and borked a chip selecting method, I have to admit, I am very glad there are some skilled and talented people here that can see and correct these silly mistakes i make LOL.

[rkauer]

Originally Posted by Zetr0

@rkauer

i find i make them all the time.... i blame my OCD... everyone whoms anyone has one

but do i really make them.... or DO i subtly place errors for people to discover eh?


yeah.... your right.... i make 'em..... I made a completely retarded a while back that only got discovered earlier,

I followed some badly drawn schematics that i was given from aminet and borked a chip selecting method, I have to admit, I am very glad there are some skilled and talented people here that can see and correct these silly mistakes i make LOL.

LOL, I think I stop to drink too much (nah! where I put my cup?).

[rave]

Best of luck with the project guys.

My hope holds out for a new 600 accelerator in my lifetime yet!!!

Big big WOOT!!!

Originally Posted by rkauer

OK, that's official. We start the project.

I'm now in the basic development of the design. The goal is a simple, albeit reliable, A600 accelerator with 4~8Mb of FAST RAM (switchable).

The project starts now (erm, almost... I need to finish the RGB>YUV inside an A520's case converter first).

ATM, I'm putting the pieces together in Express-PCB. The board will not block the HD cradle, BTW.

More details: 68EC020 (up to 28MHz, if the board runs stable). Better CPU in a future design. No PGA socket ATM, but possible in another version.

One SIMM bank to up 8Mb (better than nothing), more if a better CPU is used in the design (full 020 or any 030).

All surrounding logic will stand in a couple of CPLDs for small footprint. Dual layer board (multi-layer is very expensive!).

Less than 80 EUROS (more than this is robbery, believe me) is another main goal.

An adapter board will arise to those ppl who wants to put the accel. inside an A500/2000/CDTV. That's an easy part.

Disclaimer: no, I not will make a 060 board for A600, neither a PPC/Coldfire one. I'm will not be responsible for loosing hair, marriage breakouts, Microsoft or your cat take fire. Be warned!

Dead line: two more weeks(TM).

Hi, i'm a spanish amiga-fan, and your project follows with attention from spain too

So, do you know the Crusoe Transmeta processor? It is a processor capable of any other one behaving like by means of a programming... maybe, if it can programing his microcode like a 68000, perhaps can born a acelerator card with a "virtual" Mc68000 at 100Mhz without cooling...

Can be possible? or is a dream?

Please excuse me for my bad english sorry