10 September 2022, 10:18 | #201 | |
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Haha, that is a funny story Dread on standard A500 is ok, but with this accelerator it is perfect! Your accelerator is a true joy to use. With many games made for Scorpion Engine they usually require something like A1200 CPU specs. so there you have it |
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10 September 2022, 21:54 | #202 |
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I'll go next test it on the diagrom.
I wonder if the E clock is "ok enough" here? hm |
11 September 2022, 17:57 | #203 |
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12 September 2022, 08:28 | #204 | |
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18 September 2022, 05:29 | #205 |
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ok, it boots fine into diagrom, and all the tests pass.
if i remove the dual uart board, it stops booting to yellow screen, it boots to 2.04 screen, but doesn't see or try to boot from the SCSI card ROM. i booted a 1.3 workbench disk and ran amigatestkit; all fine there too. hm, wonder what's going on! anything else to try? |
18 September 2022, 05:29 | #206 |
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(and yes, the CIA tests all pass, both diagrom and atk)
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18 September 2022, 05:46 | #207 |
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hm, i wonder if the timing between it and buster on the a2000 is slightly whack?
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18 September 2022, 21:13 | #208 |
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Hmmm, I don't know the A2000 well enough to comment. You did do the DMA hacks? In any case you could try to boot without the ranger/fast RAM?
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18 September 2022, 23:26 | #209 |
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Yeah, DMA hacks were done. It shouldn't need the DMA hacks just to poke the autoconfig ranges.
I'm gonna go find/use my salae and see if i can capture some clock phase / buster timing snapshots. |
19 September 2022, 22:27 | #210 |
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here's some traces during autoconfig in diagrom! all done in pulseview.
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20 September 2022, 05:15 | #211 |
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here's another trace.
what's going on between as7/dtack7 and as14/dtack14? |
20 September 2022, 21:48 | #212 | |
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Dtack7 is sampled at the falling edge of the 7mhz clock to produce dtack14. This is all part of the bus logic to make the 14MHz cpu look like a 7Mhz cpu to Gary & co. That part looks fine to me. |
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20 September 2022, 21:55 | #213 |
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The second trace is interesting. There are two read cycles here with the first one asserting dtack a bit later then the second one. Both cycles finish without wait states though. Maybe that is something?
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21 September 2022, 02:56 | #214 |
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Hi all,
Total noob here. i am reasonably confident in soldering, not so much with surface mount tho. But I do want to try to build this card. The issue im having is interpreting some of the IC’s. When I search with the part number from the BOM I get a long list of IC’s that have similar numbers but seem to perform different functions. Would I be OK to order the parts below? U4,U9 CD74ACT02M96 U5 - SN74HCT74DRG4 U6 - CD74ACT112M U7 - 74HCT4046AD,112 U8 - SN74ACT08DRG4 U10 - MC74ACT32DR2G U1, U3 and U11 im OK with. Sorry if this has been covered already or am asking in the wrong place, you can blame Glen M his video inspired me to try it Thanks Mathesar for a great project. |
26 September 2022, 02:43 | #215 | |
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lemme go set it up again and include /OVR in the trace. |
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26 September 2022, 02:46 | #216 |
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it looks like /AS14 going high is asserting the flipflop /clr signals, which is clearing DTACK14? Ie, it doesn't wait for the bus to release DTACK7 before DTACK14 is released?
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26 September 2022, 18:40 | #217 |
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That's right and normal 68000 behaviour. Once /DTACK is sampled low in S4 (bus state) the CPU will continue and de-assert /AS at the end of S7. It will not wait for /DTACK to be de-asserted.
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26 September 2022, 18:42 | #218 | |
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30 September 2022, 07:37 | #219 |
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Thank you,
PCB’s are on the way and I will order the parts making sure IC's are SOIC, cant wait to give this a try. I really appreciate l for the assistance. I’ll let you know how I go. Cheers, |
13 October 2022, 18:19 | #220 |
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I'm a bit late to the party here but would this accelerator work in an A2000? Also since my soldering skills are pretty much nonexistent is there anywhere to purchase one of these pre-made?
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