1mb Amiga 500/1000 (AKA OCS) memory bus speed in mhz?

[ImmortalA1000]

Somebody told me it was 7mhz, and this is shared out on alternate cycles at 3.5mhz between chipset and CPU for Chip RAM. I always thought it was 7mhz for chipset AND CPU memory access on alternate cycles making it a 14mhz memory bus or clock doubled type system design.

Does this mean Fast RAM above the 512k Chip RAM (so 1mb A500/1000) is still read at 3.5mhz by the CPU or is it 7mhz memory access to 513-1024kb in address range of total system memory.

Sorry for such a n00b thing but I've forgotten the accurate figures and googling is not helping at all after 20 minutes.

[Jope]

If it is in the $200000 area (ie real fast ram) it is 0 wait state. If it is in the c00000 area, it can be either real fast ram (usually like this in the skinny Agnus equipped A1000 and A2000A) or as slow as chip ram (as it goes with the fat Agnus equipped A500 and B2000).

[hooverphonique]

A500 trapdoor memory is as slow as chip memory and starts at address $C00000 as Jope mentioned. Some cpu socket accelerators also provide memory at this address, but as real fast ram (just to fool games/demos that were hardcoded to use memory in this region).

[ross]

A 3.5Mhz memory bus is more than enough for 0 wait states on 7Mhz 68000.

And due to the way in which 68k accesses memory, sharing it halfway with 'another' involves practically no loss in speed.
This is what normally happens in OCS systems when the chipset is used in a 'moderate' way. On the other hand, with strong use of the Copper or video DMA or the Blitter some accesses for the 68k are inhibited. This is not the case with real fast-ram.

So beware: the internal bus is not at 14 or 7, the total bandwidth is 3.5Mhz.

[ImmortalA1000]

Thanks everybody who replied.

So on my Amiga 1000 with 1.5mb I had with 1mb Zorro 1 side expansion I guess it was always zero wait states?

[Cyprian]

it is 3.5MHz (for the Chipram and hardware registers) but from the CPU side is 1,7MHz due to the chipset needs two chipram cycles for each CPU access. the same story with A1200/A3000 and A4000

[thebajaguy]

ChipRAM Memory bus speed is ~14MHz for the 16-bit data bus OCS/ECS A500/1000/2000, or about 7MB/sec if it were a best case situation for a single bus master (other 68000 architectures). The Amiga chipset and 68000 share that bandwidth, with Agnus being the highest priority owner of the space.

With Agnus not agitated to drive higher display resolutions, the CPU gets one 7MHz interleaved access window, and Agnus gets the other 7MHz access - from that total of 14MHz worth of clocks. The net effect is each 'processor' (Agnus and the 680x0/Expansion bus) each has a ~3.5MB/sec bus throughput when you do the math.

You see this with a BusTest Benchmark against ChipRAM with very fast async-clock accelerators, and most Synchronous-clocked accelerators in a low display resolution. The native 68000 at 7MHz is a bit more burdened with longer-clock cycle instructions, and won't use every possible clock to be on the bus, so the benchmarking results will be lower.

With Agnus supporting higher display resolutions and colors, Agnus steals additional access windows from the 68000/expansion bus window by inserting waits (for the CPU or expansion bus DMA) while it does it's extra DMA read or write work.

ChipRAM on the A3000 is a 32-bit access by the CPU, so you can potentially get higher than on the 16-bit motherboards, but there are pitfalls. Both the 16MHz and 25MHz 68030 CPU have 'glue logic' to sync their clock to the ~14MHz ChipRAM space, and it's not able to burst, so there are no optimizations possible as with some FastRAM. CPU cards will also have similar limitations depending on their glue-logic design and clock speed. Expect to see ~2-4MB/sec in ideal conditions, but less as you raise the number of colors.

AGA chipset systems will have better access window performance for the CPU and Expansion bus access. The AGA chipset has wider ChipRAM bandwidth on it's side, so there is less stealing from the CPU except at the most extreme resolutions. Unless there is a lot of work being done by the AGA chipset, you can see >7MB/sec throughput with a good accelerator card and doing 32-bit accesses.

FastRAM on the Zorro I/II bus will have the same speed/bandwidth: ~3.5MB/sec potential - running at ~7MHZ.

[Cyprian]

Originally Posted by thebajaguy

ChipRAM Memory bus speed is ~14MHz for the 16-bit data bus OCS/ECS A500/1000/2000, or about 7MB/sec if it were a best case situation for a single bus master (other 68000 architectures). The Amiga chipset and 68000 share that bandwidth, with Agnus being the highest priority owner of the space.

there is no way to reach 7MB from the chip ram.
3.5MB/s is the limit in case of A500 and 7MB/s in case of 1200
You can see that in the BusTest results. If you have better figures please share BusTest screenshot.
Math is simple: 3.5MB/s divided by 2 (16bit A500 bus) is 1.7MB/s; 7MB/s divided by 4 (32bit A1200/A4000 bus) is... 1.7MB/s


Thats because the Chipram and hardware registers access are limited by low chip clock 3.5MHz

[roondar]

Originally Posted by Cyprian

there is no way to reach 7MB from the chip ram.
3.5MB/s is the limit in case of A500 and 7MB/s in case of 1200
You can see that in the BusTest results. If you have better figures please share BusTest screenshot.
Math is simple: 3.5MB/s divided by 2 (16bit A500 bus) is 1.7MB/s; 7MB/s divided by 4 (32bit A1200/A4000 bus) is... 1.7MB/s

Thats because the Chipram and hardware registers access are limited by low chip clock 3.5MHz

The Blitter (technically the whole chipset) can definitely access memory at 7MB/sec on OCS. Example, a Blitter A-D copy blit will copy @3.5MB/sec write speed if no other DMA is active. A copy is reading+writing, so 2*3.5=7MB/sec.

The reason that BusTest caps out at 3.5MB/sec on OCS is that Agnus only lets the CPU access Chip memory every other cycle (never two back to back), which halves the number. But the chipset itself can and does access Chip RAM at 7MB/sec.

That said, you are certainly correct that the Chip RAM bus runs at 3.5MHz/16 bits

[Cyprian]

Originally Posted by roondar

The Blitter (technically the whole chipset) can definitely access memory at 7MB/sec on OCS. Example, a Blitter A-D copy blit will copy @3.5MB/sec write speed if no other DMA is active. A copy is reading+writing, so 2*3.5=7MB/sec.

The reason that BusTest caps out at 3.5MB/sec on OCS is that Agnus only lets the CPU access Chip memory every other cycle (never two back to back), which halves the number. But the chipset itself can and does access Chip RAM at 7MB/sec.

That said, you are certainly correct that the Chip RAM bus runs at 3.5MHz/16 bits

well, the blitter is just a the part of the Agnus chip, it is part of its logic. Therefore in order to speed up the blitter you have to create a new, faster Agnus chip.

Regarding that "Blitter A-D copy blit will copy @3.5MB/sec write speed ", the Agnus logic limits DMA channel speed to 1,7MB/s, it means that "3.5MB/s" is just 1.7MB/s for reading plus 1.7MB/s for writting.

[ross]

Originally Posted by Cyprian

Regarding that "Blitter A-D copy blit will copy @3.5MB/sec write speed ", the Agnus logic limits DMA channel speed to 1,7MB/s, it means that "3.5MB/s" is just 1.7MB/s for reading plus 1.7MB/s for writting.

It's like roondar said.
Maybe you confused MHz and MB/s: as the bus is 16 bit, if it's @3.5MHz it's natural to get 3.5*2(byte)/2(channels)=3.5MB/s copy speed (3.5 read + 3.5 write).
Blitter is not limited like CPU to bus accesses, so if nasty mode is on it can use any cycle (A and D are different channels, so there is not back-to-back 'rule' broken).

[Cyprian]

ok, I see it now, when other DMAs are off, the blitter channel have throughput 3.5MB/s (1.7Mhz 16bit bus)

[No.3]

I also would like to know at with clock rate the Chip-Ram is running with OCS/ECS (and also with AGA), but come guys, are you serious?! 1.7 MHz, 3.5 MHz, 7 MHz...

Therefore I will rephrase the question: if you attach an oscilloscope to the Amigas chip-memory chips, which frequency will the oscilloscope show? For sure it will not jump back and forth from and to 1.7 MHz, 3.5 MHz, 7 MHz...

[roondar]

Originally Posted by No.3

I also would like to know at with clock rate the Chip-Ram is running with OCS/ECS (and also with AGA), but come guys, are you serious?! 1.7 MHz, 3.5 MHz, 7 MHz...

Several people have already pointed out the OCS Chip RAM clockspeed is 3.5MHz. There was (perhaps is) some confusion about the speed of a DMA channel vs the speed of the bus, but by now everyone agrees the clockspeed of the bus is 3.5MHz

[No.3]

And what about AGA ? AGA Chip-RAM has 4* the bandwith of OCS/ECS. 2* is due to 32 bit instead of 16 bit. But the second 2* ? Is the memory running at 7 MHz or is it still running at 3.5 MHz but with "double-data-rate" ?!

[Cyprian]

Originally Posted by No.3

And what about AGA ? AGA Chip-RAM has 4* the bandwith of OCS/ECS. 2* is due to 32 bit instead of 16 bit. But the second 2* ? Is the memory running at 7 MHz or is it still running at 3.5 MHz but with "double-data-rate" ?!

AGA is the same as OCS - 3.5Mhz for memory and hardware registers, and the CPU have every second slot - 1.7MHz.
The only difference is 32bit bus width in case of AGA vs 16bit in case of OCS

[roondar]

Originally Posted by No.3

And what about AGA ? AGA Chip-RAM has 4* the bandwith of OCS/ECS. 2* is due to 32 bit instead of 16 bit. But the second 2* ? Is the memory running at 7 MHz or is it still running at 3.5 MHz but with "double-data-rate" ?!

AFAIK (but note, I could be wrong about how the HW is implemented), the higher bandwidth is indeed due "double date rate" like features, though it could also be a simple burst read from the memory chips. Keep in mind the higher data rates only apply for bitplane fetches and sprite fetches. The Blitter/Copper/Audio & Disk still run at OCS speeds. The CPU gets the same amount of DMA slots as before as well, but they are now 32 bit wide.

The following table shows the 4 fetch modes AGA supports for Bitplanes & Sprites. OCS only supports the first of these four options. This comes from the AGA documentation you can find floating around on the net.

BPAGEM BPL32 Bitplane Fetch Increment Memory Cycle Bus Width
------------------------------------------------------------
  0      0    By 2 bytes (as before)    normal CAS     16 bits
  0      1    By 4 bytes                normal CAS     32 bits
  1      0    By 4 bytes                double CAS     16 bits
  1      1    By 8 bytes                double CAS     32 bits

[No.3]

Originally Posted by roondar

AFAIK (but note, I could be wrong about how the HW is implemented), the higher bandwidth is indeed due "double date rate" like features, though it could also be a simple burst read from the memory chips.

that's the problem, there is no explizit information how AGA achieves the 4* bandwidth over OCS.
I also read 64 bit or 7 MHz instead of the double-data-rate. But likely this are misinterpretations how AGA (and the Amiga in general (e.g. the 1.7 MHz CPU frequency crap, as I said, for sure the oscilloscope will nowhere show a 1.7 MHz frequency)) really works?!

Originally Posted by roondar

Keep in mind the higher data rates only apply for bitplane fetches and sprite fetches. The Blitter/Copper/Audio & Disk still run at OCS speeds. The CPU gets the same amount of DMA slots as before as well, but they are now 32 bit wide.

AGA is even more crazy, as Paula is still 16 Bit !?

[roondar]

Originally Posted by No.3

that's the problem, there is no explizit information how AGA achieves the 4* bandwidth over OCS.
I also read 64 bit or 7 MHz instead of the double-data-rate. But likely this are misinterpretations how AGA (and the Amiga in general (e.g. the 1.7 MHz CPU frequency crap, as I said, for sure the oscilloscope will nowhere show a 1.7 MHz frequency)) really works?!

My guess is what Cyprian means by the 1.7MHz frequency is that any given DMA channel (including, for this purpose, the CPU) can't access Chip RAM on two consecutive cycles. You could use this to argue the Amiga DMA channels run at 1.7MHz, while the bus itself runs at 3.5MHz. While I agree the bus runs at 3.5Mhz, I don't think the 1.7MHz DMA channel theory is really correct, because the DMA channels+CPU can access any of the bus's cycles, just not two in a row - which to me (as a SW not HW guy) doesn't seem to fit a 1.7MHz clock rate.

The issue is of course that from the perspective of an AGA programmer, each of the interpretations (64 bit@3.5MHz, 7MHz@32 bit, 4x16bits@3.5MHz etc) would all end up delivering the very same thing - 4x the data rate for Bitplanes & Sprites and less DMA contention for the Blitter/Copper & CPU.

Which is probably where the confusion comes from. I think it's still a 3.5MHz bus, but now @32 bits, this would seem to fit with the AGA documentation that talks about double CAS fetching.

AGA is even more crazy, as Paula is still 16 Bit !?

Yup, on AGA, Paula is 16 bit. The Copper is also 16 bits. And the Blitter is also still 16 bits.

[Cyprian]

Originally Posted by roondar

My guess is what Cyprian means by the 1.7MHz frequency is that any given DMA channel (including, for this purpose, the CPU) can't access Chip RAM on two consecutive cycles.

exactly, by "1.7MHz" I mean two consecutive 3.5MHz cycles. now I see that 1.7MHz is a bit misleading