19 April 2020, 13:03 | #101 | ||||||||||||
son of 68k
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Then what is "change" for you ? Alter something in the table itself, or switch to another one ?
Containing all information for all tasks in the system ? This is where it starts to break. Sorry, but if you have a global task, then it has to include these lists - regardless of the shape they take. You have a number of areas and a number of tasks. So you have to link them in one way or another. So you can group this info by task (usually the case) or by area, but a single mixed big list is nonsense. In a dbase this is n-to-n link. Quote:
You haven't read what i wrote, have you ? Quote:
Failure to apply security checks in time has led to security flaws in cpus, even if it's just for the speculative execution. Quote:
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And what is the exact information stored in a line here ? Does it contain all infos about all allowed tasks, or does it redirect to something else ? Quote:
That's starting to get complicated. Quote:
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Tech has evolved since... Quote:
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If only you did... Quote:
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Obviously not, but me, i have something that works. I could even show it if PM'ed. Everyone has time these days but not you ? That's very possible. Yet lack of time has always been a nice excuse to do nothing... But if you don't do it due to lack of time, nobody will. It's your idea, so you have to do it. |
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19 April 2020, 13:13 | #102 | |
Total Chaos forever!
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19 April 2020, 14:05 | #103 |
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None of this sounds like it has anything to do with any kind of Amiga.
It's just OS discussion for a non-AmigaOS, which would run on some super CPU which again has nothing to do with the Amiga except a vague passing resemblence to a strange variant of the ideas which might have gone into the 68k design... once upon a time. If your answer to the question: "If you had the chance to build a new Amiga?" is "Build something that is nothing like an Amiga" then have you really answered the question? *EDIT* It's kind of like Gunnar in this thread saying that the Blitter just isn't useful because the CPU can do the job http://www.apollo-core.com/knowledge...1&x=1&z=Uwlo2i The CPU can do every job, it's a general purpose piece of hardware, just not as well as dedicated hardware can. When asked what can be done to make the Blitter better, the answer isn't to use the CPU, it's to fix it's deficiencies and to expand on it's capabilities to keep doing things that the CPU would be much slower at! |
19 April 2020, 14:22 | #104 | ||||||||||||||||||||||||
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Please read it again. I did never say the the this 2nd level MPU chache is fast enough. I said it is big enough - so we do not need falling back to actual RAM ... and now think why I wrote "2nd" level ! Because there is a 1st level! Quote:
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Also good predictions can be made, what addresses are needed next if an instruction uses immidiates. Quote:
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The association is the other way around in the MMU case and different for every task - that is harder to cache and needs flushing (and/or tagging) of the TLB.. Quote:
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Please don’t make such false claims ... Quote:
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19 April 2020, 14:27 | #105 |
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19 April 2020, 14:39 | #106 | |||||
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A modern Amiga with custom chips and lots of power? Quote:
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I did read that post earlier and was thinking: Quote:
So what how would your Amiga look like? |
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19 April 2020, 14:40 | #107 |
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I was hoping for something that would run on a Vampire or similar: 16k code cache and 32k data cache per core x2 for hyperthreading. (The second thread runs blitter emulation on AmigaOS.) The Vampire stand-alone v4 has 512M of DDR3 RAM so 128k table size? I suppose it could be cacheable.
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19 April 2020, 14:59 | #108 | |
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We were here talking about going 64 bits or not and so we came to the specs I endet up with.. we can scale this down for something 32bit with little ram of course... With 512MB and 32KB regions we would have only 16K lines in the table .. We could reduce the entry to group-permissions only -> 16 bits per entry 32KB RAM ... |
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19 April 2020, 16:10 | #109 | ||||||||||
son of 68k
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Then there aren't less changes in your system than in the others. Because there aren't less switches.
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Therefore, when looking for one permission for one access, we have to find out in which region it belongs, and then what the permissions are. Yikes ! A typo has escaped. Let's try again : Sorry, but if you have a global table, then it has to include these lists - regardless of the shape they take. Ok so there is one permission list for every region. This appears to imply a region permissions list of variable size, as there can be any number of tasks accessing it, right ? But you suggested single list, which is this nonsense... Your post appeared to suggest otherwise... I read what you write. It's just that it's either unclear, incomplete, or wrong. Quote:
Yet you were very silent about that 1st level. Quote:
Overall, your lists will be shorter, but the valid data at one moment will be bigger because it will contain irrelevant permission values (those of not currently active tasks). Quote:
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Since when reading a whole pack of 32-bit blocks is better than finding the relevant data directly ? Well, maybe it was indeed already too complicated before... Anyway... Basically you want to replace normal paging by flat space with simple access rights. I don't think this is a good idea. It's not significantly more performant than paging (this is at least questionable), and does not provide all advantages paging does (which is a sure thing). Quote:
This makes the TLB contents obsolete. Your L1 cache will be obsolete as well. Yes there will be some flush, even if it's just the L1 cache you talk about above. In both cases, access to new data will be an attempt that will fail because nothing is in the cache in regard to it... except maybe that a regular MMU can probably do some kind of prefetching... Quote:
No, there is none. You are making the false claim. Frankly, what is the link ? You can explain or you're just asserting it without proof ? Quote:
Proof made that you have nothing concrete to show. I think i understand better now... No. As said, PM is enough. Quote:
And, by the way, why starting with the memory protection anyway ? There is a whole instruction set to design before anything is possible ! |
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19 April 2020, 16:26 | #110 | |
son of 68k
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But he's not completely wrong. Read the whole thread. A fact is that the Blitter isn't exactly fun to code on in comparison to the CPU. Another is the drawback about multitasking, even if it's a minor one. It is also true that if the cpu is fast enough so that it saturates the memory interface, the Blitter won't be any faster. And a CPU is of course more flexible. Honestly if i was against removing the blitter from the chipset, it was only for compatibility reasons. |
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19 April 2020, 20:45 | #111 | |
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It's exactly how Intel would like everything to be with the CPU doing everything (before they abandoned that idea at long last I should add). If you have a moderately powerful CPU with FastRam, and a moderately powerful chipset with ChipRam, then your Blitter can saturate the ChipRam bus and the CPU can go and saturate the FastRam at the same time. Much like a modern x86/64 has ram and the GPU has it's own pool of Gigabytes of ram. It's why when I gave my ideal "new" Amiga I avoided anything more than a bump to the next proposed chipset of AA+ with a couple of hindsight tweaks and nothing more. The Amiga is a product of it's time and the coupling of the hardware and software with that balance of mid/low CPU + chipset is what makes it stand out from the crowd. Get rid of that and you've just got yet another PC. |
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19 April 2020, 21:00 | #112 | ||||||||||||||||||||||
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And you do not need to flush the whole TLB or invalidate data, since all tasks live in the same context memory-wise, since wie are talking about a SASOS. Quote:
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Also easy to look up, since the address is real and we can use the real (linear) address as index. (minus some bits in the end) Quote:
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You draw again very strange conclusions about things I did not say anything about ... Quote:
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that is exactly the problem with the current design. For a MPU the opposite is true: it would be foolish to invalidate the whole TLB, since it probably contains permissions for often frequented regions like like eg gui-libraries, network message ports ... or the task before the active one which has high probability to me active again soon.... Quote:
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Plus you get rid of address translations and it is easy and fast to share information. It makes messaging fast and mitigates most of the overhead mentioned in the "Singularity" research paper. (they are not the only ones - this overhead is eg. the reason why projects like OSv exist and actually get used.) Quote:
no it will not - that is the whole point. Quote:
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http://libos-nuse.github.io/files/netdev01-tazaki.pdf Quote:
(they still seem to be quite high and costly https://www.percona.com/blog/2017/11...text-switches/) Quote:
(see next answer) Quote:
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Last edited by Gorf; 19 April 2020 at 22:20. |
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19 April 2020, 21:40 | #113 |
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I think what Gorf is proposing is a multithreaded single task OS. One table to rule them all. Not much to context switching because all threads share a context.
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19 April 2020, 21:51 | #114 | |
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I had to press PageDown twice to get through Gorf's latest reply. What an epic derail/exchange, reminds me of the golden years of forums, when such things were the norm
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Some sort of A1200+ACA melt would do me just fine. |
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19 April 2020, 22:06 | #115 | |
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There is actually a term for that type of operating systems, which I used here previously - SASOS: https://en.wikipedia.org/wiki/Single...erating_system Last edited by Gorf; 19 April 2020 at 22:14. |
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19 April 2020, 22:11 | #116 |
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19 April 2020, 22:32 | #117 |
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@Gorf
ACA is an accelerator brand. |
19 April 2020, 22:37 | #118 |
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20 April 2020, 09:12 | #119 | |||||||||||||||||
son of 68k
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So i kinda understand what Gunnar does, except i don't agree with his additions which are targeted toward performance only and not programming flexibility nor code density (or mere design elegance). Quote:
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So there is single data per region and therefore the access rights can not be for more than a single task or all tasks at once. No two tasks can see same region with different access level. Then what you write does not reflect what you think. Quote:
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What i wrote is precisely that current systems may well be able to not invalidate anything, hence the problem is gone ! Quote:
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So big deal, you have 0.25% loss instead of 0.5% (and i'm not even sure these numbers aren't a lot higher than the real ones). Data regarding other tasks has a lot of chances to be obsolete. Quote:
You can not quantify the gain your system can have. But what be quantified is the loss of features it involves. OSv isn't general purpose OS attempting to replace currently existing ones. Perhaps it's even dead or old, i dont know : i couldn't even find a Wikipedia page for it. So no, it's no longer relevant. Quote:
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I didn't make any assumption ! You will have the time someday, YES or NO ??? If answer is YES, then use it to produce something concrete. IF NO, you have better use of it and you're wasting it here. Tailoring a CPU toward a specific OS is a big, big mistake IMO. It ceases to be general purpose. There are things it will never be able to do (unless late additions that totally destroy the concept). |
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20 April 2020, 11:49 | #120 |
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Agree to disagree dudes, at some point you're just having a personal argument out in the open and are making it very hard for other people to get a word in. Plus the risk of causing offence just rises and rises.
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