19 November 2021, 21:26 | #141 |
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More thoughts: Your trapdoor RAM board has untapped potential as only 0,5Mbyte of each 2Mbyte chip is actually used. What about mapping the untapped memory into ZORRO II space?
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20 November 2021, 09:12 | #142 | |
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A few jobs ago (oh crap, 10+ years ago) I did a little product with microcontroller and SDcard interface. Many micros come with pretty good SD and FAT16/32 libraries. But you're getting into quite a project there. Or did you mean to do the SD software on the Amiga side? Hmmm... I left a pad for "A9" on the board, half thinking about that - but can't really imagine how - because Agnus is RAS/CASing them. Header and ribbon cable back to the CPU board? |
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20 November 2021, 11:49 | #143 | |
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You can just expand your trick to map 512K blocks into the Amiga's memory space. But instead of mapping the 512K blocks to $C00000, map them to $200000. Getting the full 2Mbyte out of the DRAM chips is tricky because of the refresh (it can be done but not with a few simple discrete chips), so we are stuck with 512 rows but we can address 1024 columns by using A9 together with ~CAS. This way we can double the amount of memory we get out of the 4 dram chips. It won't be real (as in "fast") fastram but it will be cheap! |
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20 November 2021, 11:56 | #144 | |
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It's not too difficult, I have Mika's "A500ide" running here which uses the a simple device driver written in assembly. That driver can be modified to talk to an SD card instead of an IDE device. As long as the driver allows reading and writing of 512 byte sectors it will work. (Oh and we need to fake some sector/cylinder/surfaces thing for HDtoolbox to work). And there are other open source drivers out there as well, including SD card drivers. But again, to stay in the spirit of easy DIY-able designs, it will be a pretty simple hardware interface so it will be relatively slow. |
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22 November 2021, 11:46 | #145 | |
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Maybe people would enjoy a simple microSD card interface added to your existing design. It would be the simplest accel/ram/hdd card out there. I'd build one up. |
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29 November 2021, 16:30 | #146 | |
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04 December 2021, 08:39 | #147 | |
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As soon as I have some more time I will work further on the next revision of this board. There is an SD card controller in the pipeline and I have the schematics done for a version that supports DMA to make the A590 side car work. However, that release will be beginning of next year. This month is going to be too busy for any hobby work I'm afraid. (First up is Sint Nicolaas!) |
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04 December 2021, 14:51 | #148 | |
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05 December 2021, 09:42 | #149 |
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Oke, for a super simple SPI controller using old-school 7400 logic we will have to do the bit-shifting in software. The hardware will be a just a 1-bit interface
So, the trick is in the software. What is the quickest way of shifting 8 bits into memory? What do you think of this routine (the 1-bit interface is connected to bit#7 of the IO port): Code:
;read one sector of 512 bytes to memory pointed to by (A2) Read_Sector: lea SPI,a1 ;pointer to SPI interface I/O port move.w #511,d2 ;init sector byte counter Loop: move.b (a1),d1 ;read one bit add.w d1,d1 ;shift left move.b (a1),d1 ;read one bit add.w d1,d1 ;shift left move.b (a1),d1 ;read one bit add.w d1,d1 ;shift left move.b (a1),d1 ;read one bit add.w d1,d1 ;shift left move.b (a1),d1 ;read one bit add.w d1,d1 ;shift left move.b (a1),d1 ;read one bit add.w d1,d1 ;shift left move.b (a1),d1 ;read one bit add.w d1,d1 ;shift left move.b (a1),d1 ;read one bit lsr.w #7,d1 ;shift right to right align complete byte move.b d1,(a2)+ ;store byte dbra d2,Loop rts Using a 14MHz CPU running out of fast ram we can do 107 Kbytes/s. Not too bad imho. |
05 December 2021, 11:32 | #150 | |
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I'm sure a 68K ASM wiz will come along and shave a couple of cycles off. Where in memory will SPI live? |
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05 December 2021, 11:36 | #151 | |
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How do you synchronize the spi read with the clock - is the hw generating a clock pulse each time the spi address is accessed? I suppose this interface only supports a single spi mode then |
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05 December 2021, 15:32 | #152 | |
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Edit: Oh, now I think you meant SPI modes as in clock polarity and such. Yes, only a single mode supported |
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05 December 2021, 16:33 | #153 |
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05 December 2021, 19:12 | #154 |
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74299?
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05 December 2021, 20:18 | #155 |
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05 December 2021, 20:18 | #156 |
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05 December 2021, 21:15 | #157 |
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09 December 2021, 20:37 | #158 | |
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A hardware shifter would be quicker but would also require a lot more logic chips. It's not only the shifter itself, it's also a bit counter and some logic (interrupt, flag, waitstates, etc) to synchronize shifting with cpu access (the cpu needs to know when shifting is done so it can read the data). The whole idea is to keep the hardware as simple as possible so that anyone can build it. |
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09 December 2021, 22:00 | #159 | |
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Fair approach but probably everyone capable to order PCB (as probably nobody nowadays doing PCB by himself) and solder all elements and make board run is capable to solder even 3 more IC's. Guys who prefer to buy assembled and working PCB probably don't care about 3$ more... And i have strong impression that 150KBps vs 500KBps is something worth such complication. Anyway it was just quick idea. Thank you for all work! Appreciate it very much. |
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23 December 2021, 09:27 | #160 |
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Can anyone tell where the FAST ram in the A590 / GVP HD+ and all these other side cars ends up? I assume, as they are supporting autoconfig they will end up in Zorro II space. But the SCSI part will also be mapped there.
I ask because I need to map the ranger RAM to somewhere in Zorro II space the "dirty" way (so without autoconfig) to make it DMA capable. It is probably safest to map it high up in the Zorro II space. One candidate address is $900000 to $9FFFFF, I only need to swap a few wires for that. One will have to use the addmem utility though to use it... Any ideas? |
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