SukkoPera's Open Source Hardware: A500/A600 Chip/Fast RAM Expansions

[SukkoPera]

I don't mind if people make a *fair* amount of money with my work. The community also needs builders, and the building process is easily underestimated. It needs stocking on PCBs, components, manual soldering, getting good equipment, maybe flashing some firmware, testing, packing, going to the post office and possibly queuing there, providing support, handling returns and repairs, not to mention paying taxes if done in significant numbers. The most long-sighted ones might even make contributions to the original author and or to the selling sites. The people building TFs on AmiBay do all of that excellently, they are models to follow for how to get OSHW done right. They definitely deserve some compensation.

It would really all work great, and it does in other contexts. The only reason why it does not work in retrogaming is because it is not understood, this is still my opinion.

@Lemaru: thanks for the notice, I saw he got a ton of bad reviews on his FB page. I feel a bit sorry because he had started with the right foot as far as I understand, by building nice projects and selling them correctly. Then he started self-attributing stuff and that's where he had it all go wrong. He could have just added a "Brought to you by Donny" line and it would all have been fine. But removing credits and, more importantly, license claim and project URL is definitely a no-no.

So it appears @seb132 is right, there are many good guests but a few bad guests stand out more.

Thanks for the support, I am really puzzled at how to go on.

[Lemaru]

Originally Posted by SukkoPera

@Lemaru: thanks for the notice, I saw he got a ton of bad reviews on his FB page. I feel a bit sorry because he had started with the right foot as far as I understand, by building nice projects and selling them correctly. Then he started self-attributing stuff and that's where he had it all go wrong. He could have just added a "Brought to you by Donny" line and it would all have been fine. But removing credits and, more importantly, license claim and project URL is definitely a no-no.

No worries. I hate it when people take the piss. If ever modify anyone's design, or use part of it for something I have created (be it a 3D model or PCB), I always leave credit on stuff. And put a mention/thanks on GitHub and Thingiverse pages. Those who do the work deserve the credit. At most I may add "Assembled by Lemaru" somewhere on the board if it's something I have assembled, just to differentiate ones I have built from others, which also helps when it comes to supporting stuff.

What this guy's doing is wrong, so wouldn't feel sorry for him at all.

I notice his Facebook page has now been taken down, and he has removed his page from showing in Google listings as that was getting bad reviews too.

There's alot of comments on my post on Facebook, and everyone's in agreement that he's in the wrong. He's started blocking everyone who comments on anything.

If he wasn't guilty of doing it, then he should defend himself, else he just looks more guilty.

[Lemaru]

Well it looks like he may of partially learned the error of his ways as he has now at least given credit in the comments of his Instagram posts.
It's a step in the right direction I guess.

[demon-knight]

Originally Posted by Lemaru

Well it looks like he may of partially learned the error of his ways as he has now at least given credit in the comments of his Instagram posts.
It's a step in the right direction I guess.

Ha, he blocked me from his page!

[SukkoPera]

Heh, I am still blocked as well. I hope he stated that the project is OSHW and put a link to my GitHub, otherwise I feel he's still breaching the license.

And I also help he's clearly marking it as experimental, as Matt has helped me find a crucial issue with the board that will likely give it a hard time when starting up. On the other hand, if Donny found and fixed the issue, he MUST offer his modified sources.

[MoonDragn]

This is cool. Is there any way to adapt PC Dram or DDRs into the amiga? I have so many of them lying around it is not funny. Every time I upgraded my PC there are always obsolete hardware lying around. If I could repurpose them that would be amazing.

PS... Looked these chips up, they are Dram... just 256x16 cmos dram, so I guess it is possible. I have to dig up my old dram and see if there is anything compatible. Looks like it is a matter of connecting the address bus to the chips and using a clock chip to get the timing. Interesting. Ahh I see another thread about adapting the stick mem too. I guess it is been done before just need to figure it out for myself.

[kipper2k]

I am all for an a500 with extras (basic extras). consisting of a 1 x 16Mb chip ram, 8MB Fastmem, RGB2HDMI header, onboard gotek to name a few.

Issues would be availability of an 8375 agnus so allowances would have to be made for an 8372a or equivalent. A wish list would be bootable SD or implement the IDE CPLD on the motherboard. And for the sake of compatibility make these features be capable of toggling on and off.

I don't think this is too much to ask for . So, next question is a doozie...Will it happen ?

[jbilander]

Originally Posted by kipper2k

Issues would be availability of an 8375 agnus...

Hi, regarding Agnus 8375, does anyone know the status of the Agnus verilog here?

https://github.com/nonarkitten/amiga...e/master/agnus

I did a draft on a 8375 drop in replacement in KiCad the other day. I think it can be done by designing a PCB with castellated holes on all edges to simulate the real thing you plug into the socket. First I was thinking this would be a perfect job for a Microchip ATF1508AS CPLD since it is 5V (and drives 5V IO as well) but then I thought some more and realized that it's probably too small in terms of number of cells to synthesis the verilog, the Amiga is probably fine with 3.3V IO anyway and also you would probably want a couple of built-in PLLs to mul the 28M clk, a quick glance at the code shows 2X and 3X, so a small FPGA is probably what should be used which also would future proof the design better. Since all FPGAs nowadays are at maximum 3V3 we need translation. I came up with this solution using four sn74cbtd16210 chips, they are 20-bits each so it is a perfect fit for the 80 pins that need translation. Every single pin gets used, 4 pins are VCC/GND. The design I was thinking of is the pics below, the four ICs will go on the backside of the PCB facing down to the motherboard when put into the socket. The height of the sn74cbtd16210 is 1.20 mm which is probably fine thinking of where the socket pin sits.

I briefly routed the four chips to get a feeling if this all can be done and I think it can. On the front side I imagine a FPGA chip, a voltage regulator and a bunch of caps. What do you guys think? Is it worth pursuing this further? What FPGA to use?. I'm thinking small, easy to solder and relatively cheap. Perhaps something like a 10M02SCE144C8G or any of the cheap Lattice series FPGAs.

[hooverphonique]

Interesting idea - you could try having a bare pcb (castellations only) made to see if it connects correctly to the socket with a 1.2mm spacer underneath..

[kipper2k]

any drop in replacement or even something that is made for a replacement motherboard is definately welcome

[SukkoPera]

This sounds like a great project and I'm sure it would be very well received! The only issue I have with these reimplementations is that they always involve some guesswork, which will create inaccuracies and/or bugs.

IIRC Stephen Leary was working on a similar project right before he left the scene, so I don't think it will happen, but I think he had got hold of some C= internal docs that detailed the Agnus design. I'm not sure whether those docs are easy to find, but they could be the key to making a *perfect* implementation.

On a side note, there could be multiple versions of this: a straight 8375 replacement and an 8375 with an 8372-like pinout, to use on older mainboards, even though I'm still not sure it would be easy to get them to 2 MB of chip RAM.

Keep it up!

[Lemaru]

Stephen's Agnus replacement has been picked up by Renee Cousins so it should be in the pipeline. They have their hands full with the Buffee CPU replacement first though.

[jbilander]

The link I posted above is her github repo. In the Agnus folder is a couple of pdfs that looks to be original from C=. I guess that is the very same docs we are talking about. I think Stephen's design was of the kind "desolder the old socket and replace with the new board". I'm thinking first we could try if a drop in replacement PCB can be designed and avoid TH on new designs. It will be very limited in size though so probably need to go BGA on the FPGA chip which I would prefer not to. I tested a design with a 20 x 20 mm 10M02 and there is not enough room for voltage regulator and caps. As nonarkitten states in the readme: The PLCC socketed PCB for Agnus will present a unique engineering challenge.

Edit: this is how it looks with a 11 x 11 mm BGA (13x13 layout)

[Mathesar]

Do we need the commodore docs schematics? We know exactly what is inside Agnus right?
Just a bunch of counters / adders and some multiplexers. Copper is easy, Blitter is a bit more complicated.
But code for this exist in the MiniMig sources. The only challenge is to interface/adapt this code so it actually works with real Amiga bus timing and signals.

[jbilander]

so I did some more work on this one. Looks like I got the design down on four layers with a 3V3 filled zone under the BGA on the VCC-layer, but I have no idea if this will actually work. I got some feedback from Niklas too, thanks. It is still very much a prototype where the concept yet remains to be verified in a POC.





The PCB is very crowded, tracks are 6 mil and since JLC doesn't support micro/buried vias I did the BGA-fanout with 0.45/0.2mm vias which is just about borderline what JLC can do. It makes the GND-layer look a little like "Swiss cheese" with a lot of holes under the BGA-chip so not optimal but not too bad I think. My intention is to make this open hardware eventually, just need to figure out what license to use for this. I have never done a PCB design with castellated holes (plated half-holes) before so feedback is welcomed. I read JLC has the requirement that the hole size and space need to be 0.6 mm at least, https://jlcpcb.com/quote/pcbOrderFaq...llated%20holes ,this requirement is met by my design but then googling a little I saw this https://www2.hdl.co.jp/en/plcc68-series/ap68-08-m.html thinking perhaps that approach would be an even better design, if JLC can produce such "PCB-pins" I don't know, and if so how fragile those "pins" are.

I'm still a little unsure about what dimensions to use for the PCB. I checked the Agnus docs and from what I can see the C= specification (sheet 17 of 50) says 1.9 inch, that must be a typo and it should be 1.19? 1.19 x 25.4 = 30.226 mm. That is what I used now in my KiCad-drawing. Checking the 84-pin PLCC Microchip ATF1508AS pdf on page 26 it says Min 30.099 mm, Max 30.353 mm. Calculating the average (30.099 + 30.353)/2 = 30.226 reinforces my believe that the Agnus spec should really say 1.19". Also checking with a digital caliper on a real Agnus shows numbers close to that.

The current design is made for the Intel Max 10, 10M02SCU169C8G FPGA 130 I/O 169UBGA, or its pin compatible bigger brothers same form factor also using 169UBGA, the footprint in KiCad is BGA-169_11.0x11.0mm_Layout13x13_P0.8mm_Ball0.5mm_Pad0.4mm. The FPGA should be straight forward programmable with a standard USB-blaster using JTAG and Quartus. This will be a little tricky one to solder but I think it can be done with hot air and using the kapton tape trick to hold the chip boxed in a corner while soldering, like this: [ Show youtube player ] and for soldering the smd stuff Marc Siegle has us covered to do this professionally: [ Show youtube player ]

Still remains to investigate if the 1.20 mm elevation of the PCB (caused by the N74CBTD16210DGGR chips) is going to be a good fit in the PLCC-socket or not.

I thought a bit about designing a "one Agnus to rule them all" with jumpers to decide if you want the 8372B or 8375 but then after realizing how crowded the PCB got and the differences with pin 41 (TEST vs GND) and 42 (GND vs DRA0) https://en.wikipedia.org/wiki/MOS_Technology_Agnus .I now think it is easier and perhaps better to have different PCB:s for this to avoid people accidentally releasing the magic smoke with a wrong jumper setting.

I have also thought about how to control whether the chip should startup in PAL or NTSC-mode especially for the 8375 since it doesn't use Test-pin 41 for this. If a jumper is needed to control this I got an idea that maybe an NC-pin in the JTAG-header can be used for this purpose, pin 6,7,8 are NC and me thinking pin 8 would be a good candidate since it's next to pin 10 which is GND. In that case a standard 2.54mm jumper could be used to control this. e.g. jumper on = GND = NTSC, jumper off = PAL (pulled up by a 3V3 10k pull-up resistor, track routed to a free IO-pin used for startup mode detection in verilog). I don't know if this strategy of (re)using pin 8 for this purpose will work.

[SukkoPera]

You rock, man! I think this deserves a thread of its own though, most people won't notice it here.


My friend @majinga had the same idea with castellated holes for an Agnus replacement, but I don't think he ever brought it further. I'll try to point him to this thread in the hope he can help with the dimensions.

[1NOM155]

Wow what amazing.

I dont if someone already propose, in any case, to gain more space for the pcb agnus replacement, could be possible to create a pcb with pins to solder directly on the old socket position?

Sent from my TA-1004 using Tapatalk

[SukkoPera]

Something I wanted to mention is that maybe you can use a smaller 3.3V regulator: how much current does the FPGA need?

[LIV2]

Great work with that Agnus project!

Re: the ram board ive finally gotten the right parts this week and will try on the weekend but I'm 99% sure it is all good as it worked for me already with slower parts.

[jbilander]

Thanks for the kind words. I don't know about the current draw, I guess the reason for using a smaller voltage regulator would be to get more room for debug/test-pins from the FPGA, there is only one right now, however adding more is not so easy because the remaining free BGA IO-pads are mostly all boxed in.

I did a quick test today using Pin 8 in the JTAG-header with a 10k pull-up resistor and a LED-blink program, jumper off = blink fast, jumper on = blink slowly. It seems to work just fine, the USB-Blaster doesn't seem to care about that pin at all when programming via JTAG so it can most likely be used for e.g. NTSC vs PAL mode detection.

https://imgur.com/DCMRyC9

https://imgur.com/JnN6DTt

I have now made the repo public, it is available on my github. Hopefully it'll benefit the Amiga community and people who build on this will respect the license and share their work back to the community.