Creating a new 020 accel board for A600 (eventually to A500 too)

[Zetr0]

@nandove

hello therem

welcome to the EAB, there is plenty of mischief to get up to around here, so please enjoy your stay

Thank you very much for your support in this project

for those wishing to read more on what the Crusoe is about

http://en.wikipedia.org/wiki/Crusoe

http://arstechnica.com/articles/paedia/cpu/crusoe.ars

and

the official site

http://www.transmeta.com/corporate/p...om/awards.html

----------------

for those that dont know, the Crusoe Transmeta uses CMS (Code morphing software) to translate binaries (x86 or what ever really) to VLIW (very long instruction words) that can then be processed.

A lot of companies are suing these in note books / mobile pda's etc, like Toshiba, Fujistu etc.

I will have to look into the CT employment of 68k binaries, as this would be incredibly cool, at present they have clock rates up to 1.5Ghz available for the home market.

The real trick would be interfacing this with the existing port(s) sockets of the Amiga.

Thanks for the query and suggestion

[rkauer]

Originally Posted by nandove

Hi, i'm a spanish amiga-fan, and your project follows with attention from spain too

So, do you know the Crusoe Transmeta processor? It is a processor capable of any other one behaving like by means of a programming... maybe, if it can programing his microcode like a 68000, perhaps can born a acelerator card with a "virtual" Mc68000 at 100Mhz without cooling...

Can be possible? or is a dream?

Please excuse me for my bad english sorry

Met@box???? No way!!!

Reasons:

- hard to get the documentation, more pins than necessary (adding much more complexity to the design);

- Not a huge gain of speed compared to a 030@28MHz (6x over a 8MHz 68000), hypothetically 10x using that Crusoe. Too much headache for a minor speed gain;

- Hard to design from scratch, instead those proven (albeit old) 68k designs (who are our start-point);

- Since the Crusoe don't have a built-in RAM controller nor other desireable feature, I'll stick with the 020/030.

[Stedy]

@Thread,

A few additional considerations. :P

If you are thinking of SDRAM, look at this PDF application notehttp://www.xilinx.com/support/docume...es/xapp394.pdf . You can also download the VHDL source code.

Note, you will need a device with an I2C interface to read the SPD PROM of a DIMM module. Choose your preferred microcontroller for that job. All it has to do is read the I2C interface, extract the RAS/CAS settings and memory size and pass this info to the memory controller. If there is large enough PLD, you could include the I2C interface.

SDRAM will be no quicker than EDO RAM at these speeds (upto 28 MHZ?) but is cheaper, larger memory and more widely available.

If you run the accelerator card at 7/14/28 or 56 MHz it will be the most efficient as it requires less wait states to access the Amiga CPU bus.

Please re-check the following statements

You may think 33 MHz is faster than 28, it is not. With a 7 MHz/142.8 ns bus you get to access the bus every 4 clock cycles (571 ns). For a CPU running at 28 MHz/35.7 ns that equates to every 16 clock cycles or 571 ns.

If the CPU runs at 33 MHZ/30 ns, it still has to wait 571ns or 19 clock cycles to access the bus. So although the CPU runs quicker, it spends longer waiting to access the CPU bus. Of course, the fast RAM can be accessed much quicker, hence it's name.

Oh finally, if adding a clockport, use the CPLD to implement the address decode and create the appropriate signals.

Are you planning to use surface mount or through hole technologies for this board?

Bye,

Ian

[Zetr0]

@Steady

I think to begin with for the prototypes to get each stage up, it will most likely be through hole,

then when its all implelemented in a larger CPLD it will shoot down to SMD, now i know that some through hole connectors change / delay the access timings by impedance, but as to what and how much I am unsure.

Again

you thoughts, Info and support is awesome!

I would love to eventually implement an SDRAM controller, that would be fantastic!

[rkauer]

Originally Posted by Zetr0

@Steady

I think to begin with for the prototypes to get each stage up, it will most likely be through hole,

then when its all implelemented in a larger CPLD it will shoot down to SMD, now i know that some through hole connectors change / delay the access timings by impedance, but as to what and how much I am unsure.

Again

you thoughts, Info and support is awesome!

I would love to eventually implement an SDRAM controller, that would be fantastic!

Fantastic, indeed.

But I think we don't have a gain in performance using it. Only more RAM available (who is not a bad thing). We shall see when the designs starts to galore its way out of our brains.

Right now, I'm starting the sketches for the 68k interface. And another simple idea: start the design from an already made A1200 accelerator (pin pointing the differences between it and the 68000 pins/behaviour).

[FrenchShark]

@rkauer, zetr0,

why not using an FPGA for the 68k and the SDRAM controller ?
You can use a EP3C5 (Cyclone 3 with 5000 LEs), the TG68 from tobias takes only 4000 LEs. You have 1000 LEs left for the SDRAM controller. The PLL in the FPGA is used to generate a multiple of 7 MHz -> your chip RAM accesses will be optimized since the FPGA CPU is synchronous.
You also need a serial flash for the configuration and a 16-bit SDRAM chip that you put under the FPGA (I have done design like this with a 2MB 16-bit ZBT SSRAM running at 66MHz like a charm).
For the 3.3V -> 5V, you can use a fast bus switch from NXP (CBTD3384), TI (SN74CBTD3384) or Pericom (PI5C3384).

A quick BOM from Digikey :
FPGA EP3C5E144C7N : $15.30 (by 1) -> fastest grade in a EQFP-144, 94 IOs. Enough for the 68000 bus and the SDRAM.
Flash EPCS1 : $3.50 (by 1)
SDRAM 32Mx16 133MHz MT48LC32M16 : $23.74 (by 1) -> 64 MB of fast RAM !
SN74CBTD3384 : $0.64 (by 1) -> mosfet switch used as level shifter, sub-nanosecond delay.

Voltage regulator are also needed :
5V -> 3.3V 500mA to 1A
3.3V -> 2.5V 100mA
3.3V -> 1.2V 300mA

Regards,

Frederic

[rkauer]

Originally Posted by FrenchShark

@rkauer, zetr0,

why not using an FPGA for the 68k and the SDRAM controller ?
You can use a EP3C5 (Cyclone 3 with 5000 LEs), the TG68 from tobias takes only 4000 LEs. You have 1000 LEs left for the SDRAM controller. The PLL in the FPGA is used to generate a multiple of 7 MHz -> your chip RAM accesses will be optimized since the FPGA CPU is synchronous.
You also need a serial flash for the configuration and a 16-bit SDRAM chip that you put under the FPGA (I have done design like this with a 2MB 16-bit ZBT SSRAM running at 66MHz like a charm).
For the 3.3V -> 5V, you can use a fast bus switch from NXP (CBTD3384), TI (SN74CBTD3384) or Pericom (PI5C3384).

A quick BOM from Digikey :
FPGA EP3C5E144C7N : $15.30 (by 1) -> fastest grade in a EQFP-144, 94 IOs. Enough for the 68000 bus and the SDRAM.
Flash EPCS1 : $3.50 (by 1)
SDRAM 32Mx16 133MHz MT48LC32M16 : $23.74 (by 1) -> 64 MB of fast RAM !
SN74CBTD3384 : $0.64 (by 1) -> mosfet switch used as level shifter, sub-nanosecond delay.

Voltage regulator are also needed :
5V -> 3.3V 500mA to 1A
3.3V -> 2.5V 100mA
3.3V -> 1.2V 300mA

Regards,

Frederic

I think you have a point, mister!

Those FPGA are cool! And makes the design a lot smaller. If we can grab the Verilog source and translate it to use in the EP3C5, I think we have a winner!

Just need to be sure if the code will behave like a real CPU. "Clocked" in 300MHz . Even if we achieve a "68000" running in, said, 50MHz, we'll have an excellent overall performance.

Shame we can't have a 020 or 030 "hardware-CPU emulator"... yet.

[rkauer]

Shame the FIM package don't have enough I/O pins for our needs...

And it's expensive, too...

[coze]

another problem with FPGAs is I guess most come in BGA package which I imagine impossible to solder/work on without a professional station and experience ... If there's an FPGA which comes in an easier package please do let us know

[rkauer]

Originally Posted by coze

another problem with FPGAs is I guess most come in BGA package which I imagine impossible to solder/work on without a professional station and experience ... If there's an FPGA which comes in an easier package please do let us know

http://www.customcircuitsolutions.com/fim-ep3c5.html

But as I said before, it don't have enough I/O pins...

[coze]

WOW it looks great but yeah 44 pins is nowhere near enough. Also little tad bit on the expensive side.

XDDD Already I supposed that my idea was unrealizable, but for exposing it wasn't losing anything. Anyway I will follow with many Attention your project.

[FrenchShark]

Originally Posted by coze

another problem with FPGAs is I guess most come in BGA package which I imagine impossible to solder/work on without a professional station and experience ... If there's an FPGA which comes in an easier package please do let us know

The EP3C5 comes with a EQFP-144 : quad flat pack 144 pin with an additional ground pin under the chip, pitch : 0.5 mm.
It is doable. I have used an EP3C10 EQFP-144 on a design few months ago.
To solve the issue with the central ground pin, I put a square pad with a hole so I can solder it from under.
If 94 IOs is not enough, you can share the data bus between the SDRAM and the 68000 connector. You can even share the address lines if necessary (freescale does it on some of its coldfire CPUs).
With the remaining IOs, adding a (high-speed) IDE bus on the board might be possible.

Regards,

Frederic

[FrenchShark]

Originally Posted by rkauer

I think you have a point, mister!

Those FPGA are cool! And makes the design a lot smaller. If we can grab the Verilog source and translate it to use in the EP3C5, I think we have a winner!

Just need to be sure if the code will behave like a real CPU. "Clocked" in 300MHz . Even if we achieve a "68000" running in, said, 50MHz, we'll have an excellent overall performance.

Shame we can't have a 020 or 030 "hardware-CPU emulator"... yet.

The TG68 from Tobias actually executes one instruction in two cycles. So it 2x faster than a regular 68000 at the same frequency.
My guess is that we can run it at 28 MHz at least.
The FPGA gives you a lot of freedom : for example you can easily put a block RAM that catches on the fly the CPU accesses to the chip registers : you have an action replay for the same price.
The PLL is programmable so you can throttle up/down the CPU speed to stay compatible.
It is the perfect WHDLOAD accelerator.

Regards,

Frederic

[FrenchShark]

Hello,

I have just checked the IO requirements.
If the data bus is shared, you need 80 IOs for the CPU and the SDRAM, leaving 14 IOs for something else such as : audio output, PS/2 connector, SD-card, ...
Moreover, the EP3C5 and EP3C10 are pin compatible, so we can have second version with the same PCB and an EP3C10 that has more functionalities (ex : DSP + audio + SD-Card).

What do you think ?

Frederic

[rkauer]

Originally Posted by FrenchShark

Hello,

I have just checked the IO requirements.
If the data bus is shared, you need 80 IOs for the CPU and the SDRAM, leaving 14 IOs for something else such as : audio output, PS/2 connector, SD-card, ...
Moreover, the EP3C5 and EP3C10 are pin compatible, so we can have second version with the same PCB and an EP3C10 that has more functionalities (ex : DSP + audio + SD-Card).

What do you think ?

Frederic

Good point, but sharing the data bus will bring more problems in the design. Better have another CPLD with enough pins (QFPGA, of course) or use a real 68k chip (the cheaper, the better).

OR use the CPLD only for the actual CPU emulation. Lots of extra space inside. Shame SATA use a lot of the space inside the chip for it alone...

BTW: Audio??? I think Paula is good enough for an A500/600. But if you mean MP3 decoding.... Hmm........... I like the sound of this idea!

[Zetr0]

I think once we have a working accelerator up, we can look at adding a full feature port, in this way we can then add to it what one could imagine

I love the idea of mp3 perhaps even video decoding, that would be awesome!

the FPGA's will certainly be handy indeed for that, as well as other possibilities, however I do like the fall back to a native 68k series moto

[Hungry Horace]

some of us audiophiles would be more interested in even single stereo-channel AHI output than mp3 decoding tbh... -ahem-


oh wait, that's what i want on my a1200 clockport,

[Charlie]

Cool project chaps.

[FrenchShark]

Hello,

I have just looked at the A500 motherboard on the big book of amiga hardware. Since the 68000 is located close to the edge of the MB, it is pretty easy to make an adapter for the stratix board (the dev board has 80 5V tolerant IO pins).
This way, I can spy the 68000 running (the FPGA acts as a logic analyzer), then, I can replace it with the FPGA on the dev board.

So I am looking for an A500 motherboard (I only owned A2000s and A1200s).
I live in the US (Huntsville, AL).

Regards,

Frederic