22 June 2024, 10:50 | #1 |
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A500+ mystery issue - help please!
Hi,
I have an A500+ board that is behaving strangely, when I boot it using diagrom it fails all memory tests, when diagrom starts to write different values to addresses every one fails. It will always read the same values for a given address no matter what it is trying to write. The upper 16bits are different to lower 16 bits. Using the scope a noticed CAS_U and CAS_L and WE were at about 4v and struggling to be pulled down to ground to produce a square wave, there is a very small square wave (vpp 700mv). I traced these signals back to Angus. Looking at the Agnus block diagram I noticed A19 looks likes its an input into CAS generation, A19 has the same flattened square wave signal along with A17,A18,A20, and A23. A1-16 have normal 4.7v vpp square waves. The agnus socket is new, I replaced U10, U12, and U13, not U11 and replaced U34, U35 and U32, the Gary socket is also new. All custom chips and the CPU are known good and work in other boards. Not sure what else to try apart from replacing every DRAM, but not sure this is the issue here. Does anyone have any ideas on what I can try next? Thanks |
22 June 2024, 12:15 | #2 |
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Could you post a picture of the dodgy square wave?
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22 June 2024, 12:25 | #3 |
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Yes sure, here is an image of the CAS signal
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23 June 2024, 09:17 | #4 |
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It looks like it's being pulled up to vcc, what is the resistance between cas and vcc? I have an A600 on the bench and it shows >2MOhms to vcc (and gnd).
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23 June 2024, 11:44 | #5 |
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Are any of the ram or logic chips getting hot . Pulling signals up to that level will generate some heat .
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23 June 2024, 11:49 | #6 |
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Next question was going to be - have you got access to a thermal imaging camera
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23 June 2024, 13:45 | #7 | |
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Quote:
I am not sure how 1 faulty DRAM will cause the CAS signal to look like it does, also the WE signal looks the same. My logic is U11 is faulty then the (lower half of RAM would be effected, DRD0-7) and show up in Diagrom output Last edited by stevew; 23 June 2024 at 13:52. |
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23 June 2024, 13:47 | #8 |
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23 June 2024, 13:47 | #9 |
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24 June 2024, 21:57 | #10 |
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I also checked LDS and UDS signals as I believe these are used by Agnus to generate CASL and CASU, the signal on these looks okay. AS and ROMEN I think are okay. Wondering if Gary generates these signals....
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26 June 2024, 12:14 | #11 |
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https://gamesx.com/wiki/lib/exe/fetc...ice_manual.pdf
https://archive.org/details/A500_Tra...e/n51/mode/2up A couple of links I stumbled on at the weekend - may be of use to you. |
26 June 2024, 21:49 | #12 | |
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