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Old 17 April 2022, 14:15   #1
TEG
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Question about slow RAM

There's something not clear for me about this slow ram on the A500.

Correct me if I'm wrong.

1/ Slow ram exist because this memory is connected to the physical chipset bus (the bus being accessible through the A500 trapdoor) and so access by the processor on this bus are shared with chipset access.

2/ More than 512Kb extensions exist (A502 or A580 for example).

Does it mean that all this RAM will be slow RAM? I was in the idea, in my Amiga years, that only the first 512Kb expansion would be slow RAM. Thanks for the disambiguation.
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Old 17 April 2022, 15:23   #2
SpeedGeek
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Slow-Fast RAM is typically what you got with a 512KB Fat Agnus chip and a 512KB trap door RAM expansion installed. There were some early A2000s which were functionally the same with a 512KB Fat Agnus and 1MB of motherboard RAM.

This was also called $C00000 RAM in reference to the address space of the Slow-Fast RAM. Since this RAM is controlled by Fat Agnus it functions at the same speed as Chip RAM.

When the A500 or A2000 was upgraded to a 1MB Fat Agnus the systems have a full 1MB of Chip RAM and the Slow-Fast RAM disappears.

NOTE: A 512KB Fat Agnus is also known as an OCS chip and a 1MB Fat Agnus is also known as an ECS chip.

Last edited by SpeedGeek; 17 April 2022 at 15:30.
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Old 17 April 2022, 21:25   #3
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Yeah but you don't answer my question. What you get when you install a 2MB extension like the A502 in the trapdoor of an OCS A500?

512KB chip + 512KB slow + 1.5MB fast or 512KB chip + 2MB slow?
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Old 18 April 2022, 00:25   #4
Matt_H
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Quote:
Originally Posted by TEG View Post
Yeah but you don't answer my question. What you get when you install a 2MB extension like the A502 in the trapdoor of an OCS A500?

512KB chip + 512KB slow + 1.5MB fast or 512KB chip + 2MB slow?
512K of Chip + 512K of Slow and the rest is Fast.
The trapdoor bus can only address 512K. Whether that’s mapped to Chip or Slow is a function of Agnus and jumpers. Any trapdoor expansion offering more than 512K is putting the balance of the RAM on a different bus, e.g., Fast RAM (usually via a Gary adapter). It just happens to be physically located in the trapdoor; electrically it’s somewhere else.
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Old 18 April 2022, 15:30   #5
TEG
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Quote:
Originally Posted by Matt_H View Post
The trapdoor bus can only address 512K.
This what I understand too as there is 9 pins for the address bus: DRA(8:0) on the CNX connector.

Quote:
Originally Posted by Matt_H View Post
Any trapdoor expansion offering more than 512K is putting the balance of the RAM on a different bus, e.g., Fast RAM (usually via a Gary adapter). It just happens to be physically located in the trapdoor; electrically it’s somewhere else.
For the A502, after reviewing it, I understand. There's a trick. It provide 512KB for the A500. The 2MB mentioned must be for the A500+.



But for the the A580, how it work? I see on the photo a 2 wires cable to connect to Gary so I guess it's to have 11 lines address bus and so to be able to manage 2MB but still my question: how it can be fast ram, as you mention, as it use the physical chip bus??
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File Type: pdf A500_memory_diagram.pdf (226.0 KB, 56 views)

Last edited by TEG; 18 April 2022 at 15:47.
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Old 18 April 2022, 15:42   #6
Toni Wilen
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Anything in A500 trapdoor is always chip ram or slow ram. CPU read/write accesses are still going though Agnus (and are also refreshed by Agnus).

Gary adapter only changes which trapdoor 512k "bank" is selected, allowing more than 512k RAM.
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Old 18 April 2022, 15:45   #7
pandy71
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Quote:
Originally Posted by TEG View Post
This what I understand too as there is 9 pins for the address bus: DRA(8:0) on the CNX connector.

But for the the A580, how it work? I see on the photo a 2 wires cable to connect to Gary so I guess it's to have 11 lines address bus and so to be able to manage 2MB but still my question: how it can be fast ram as it use the chip bus??
Issue is Data Bus - isolated (trough 74244 + 74373 and named in Amiga as DRD), shared by CPU and chipset and controlled by Agnus. This is what make CPU access slow. There is no issue to use this address space in similar fashion as FAST RAM so even Slow (a.k.a. BOGO) RAM can be fully available to CPU - just physical RAM must be connected to D data bus not DRD data bus... And usually all this additional wires provide missing address lines with some control.
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Old 18 April 2022, 19:39   #8
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Any trapdoor memory is controlled and refreshed by Agnus if it lives in chipram address range or $C00000 range.

The original $C00000 memory was known as Ranger memory and was real fast memory for the A1000 in one or more expansions. Then the A2000 (i.e. the German one) had real fast $C00000 memory in the cpu slot. There is also one new cpu card - can't remember which or if 500 or 1200 - that can add real fast IIRC. If you get far enough to run SetPatch you can use an mmu tool to map in memory at $C00000.

$C00000 is one of the address ranges reserved for memory and which Exec will search for.
Note though, even if it is not chipram some/all(?) of it is AFAIK seen by the blitter and can make for some incompatible programs(demos) that make too many assumptions. (Toni can correct here!)
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Old 19 April 2022, 09:28   #9
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Quote:
Originally Posted by NorthWay View Post
$C00000 is one of the address ranges reserved for memory and which Exec will search for.
Note though, even if it is not chipram some/all(?) of it is AFAIK seen by the blitter and can make for some incompatible programs(demos) that make too many assumptions. (Toni can correct here!)
If you have a 1MB Agnus, then the Agnus can use the first 512k of trapdoor memory as Chip RAM regardless of your motherboard's jumper configuration.

It will show up at different addresses for the CPU and Agnus, but it is doable.

I'm not sure if it's really worth the effort of coding for this setup for more than a proof of concept.
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