DMA cycles - lack of clarity

[Herpes]

HI!

One would mean that the stuff in HRM is explained so well that everyone can understand it - but I'm sorry to report I don't get it 100%. I am still a blockhead

As I understand a raster-line lasts about 63,6 µs (this is NTSC) - this can be easily determined by (1/60Hz)/262 lines. Since in HRM the examples are for NTSC I also use that.

227.5 slots are are available for display & non-display time.
226 can be used by different devices: 4 mem-refresh, 3 disk, 4 audio, 16 sprites, 80 bitplane.
==> this would leave: 226-107 = 119 slots free for blitter, copper and CPU.

According to HRM's "DMA Time Slot Allocation" bitplane DMA starts at $30 or $38 depending on the resolution and the needed datafetch values in blocks of 8 slots.

* using 6 planes in 320 horizontal - an 8-block of slots looks like:

|_|4|6|2|_|3|5|1| ... 2 free slots for CPU, blitter, copper
20 words by 6 planes = 120 slots used ==> 50% free slots stolen by BP-DMA

Q1: in HRM it is written that these 6 planes need 160 slots - I hope this is a typo, right - or do I miss something?

* using 4 planes in 640 horizontal - an 8-block of slots looks like:

|4|2|3|1|4|2|3|1| ... 0 free slots for CPU, blitter, copper
40 words by 4 planes = 160 slots used ==> 100% free slots stolen by BP-DMA


* deducing the timing for
-5 planes in 320 horizontal - an 8 block of slots looks like:

|_|4|_|2|_|3|5|1| ... 3 free slots for CPU, blitter, copper
20 words by 5 planes = 100 slots used ==> 25% free slots stolen by the BP-DMA

- 4 planes in 320 horizontal - an 8 block of looks like:

|_|4|_|2|_|3|_|1| ... 4 free slots for CPU, blitter, copper
20 words by 4 planes = 80 slots used ==> 0% free slots stolen by the BP-DMA

Q2: is this correct along general lines or did I miss something?

Q3: is the blitter bound to operate during the "visible" time of the rasterline - or does it also copy words during vertical blank?
So the min. of vertical blank for NTSC is 20 rasterlines; for PAL the min. is 25 rasterlines. ==> is here only the CPU allowed to work on the memory or also the blitter?

Q4: Does that mean if I deactivate sprite DMA, disk DMA, audio DMA; use hires 4 bitplanes I have 226-160-4 = 62 slots free where the CPU can take only the even slots; the Copper only odd and blitter even and odd?
==> this means the blitter potentially has a theoretical max. time of 62*280ns = 17,36µs - if NO CPU or copper needs DMA (which cannot be since we need to setup the BPPT for the 4 planes with copper and initialize blitter if it should be used for copy).

The blitter is capable of doing a simple AD copy with 28,36 pixel/µs => ~492 pixel per rasterline => ~ 61 bytes per rasterline = ~ 30 words per rasterline.


Q5: how long is the horizontal blanking for NTSC/PAL - could not find info about that.

@TLDNR:
Sorry - could not find a shorter way to form my questions.

Thank you for your help!

[Toni Wilen]

1: It is technically correct, it means 320 pixel lores equals 160 slots but not all are used by bitplane DMA.

2: Looks correct. (but check 4)

3: Vertical (or horizontal) blanking makes no difference to DMA slot usage. (Exception: bitplane and sprite DMA is always disabled during last line)

4: "CPU only uses even-numbered memory access cycles" is wrong. CPU can use both but generally it uses even only because refresh or odd DMA cycles will "force" CPU to "align" with even numbered cycles and also most instructions' cycle usage is divisible by 4. (1 DMA cycle = 2 CPU cycles)

Note that there is some special cases at the end of scan line, (at least on PAL), last odd cycle is not always available for anyone. (If copper wants it, no one gets it!)

5: Who cares, it has no effect on timing (should be same as PAL or NTSC standard says)

It is better to base all calculations in DMA slots. Use of TV signal timings (scanline length, vblanking length etc..) isn't accurate for cycle timings.

[Herpes]

Tony, thank you very much for your comments - that helped me a lot for now!

[mc6809e]

For CPU timing and slot usage, it's easiest (for me at least) to see the 68000 as needing two CPU cycles to put the address on the address bus and two more CPU cycles to transfer the data into or out of the CPU, where two CPU cycles are one memory access slot. The CPU can place the address on the bus at any time, taking two CPU cycles, including the time when other DMA is occurring, but Agnus will pick the next available two CPU cycle memory access slot used to transfer the data. This might happen in the two CPU cycles immediately after the address is placed on the bus or it might be many cycles later.

[pandy71]

Originally Posted by Herpes

Q5: how long is the horizontal blanking for NTSC/PAL - could not find info about that.

For Agnus 8371 HSync pulse is lenght 17 CCK (4.79uS).

[Toni Wilen]

Agnus datasheets (eab file server should have them) have quite nice PAL and NTSC vhsync/hsync timing diagrams.

[dissident]

Originally Posted by Herpes

Q4: Does that mean if I deactivate sprite DMA, disk DMA, audio DMA; use hires 4 bitplanes I have 226-160-4 = 62 slots free where the CPU can take only the even slots; the Copper only odd and blitter even and odd?

Originally Posted by Toni Wilen

4: "CPU only uses even-numbered memory access cycles" is wrong. CPU can use both but generally it uses even only because refresh or odd DMA cycles will "force" CPU to "align" with even numbered cycles and also most instructions' cycle usage is divisible by 4. (1 DMA cycle = 2 CPU cycles)

Does that mean the blitter uses odd and even-numbered memory access cycles during his blits like the CPU could?

That would confirm my theory that the sprite-DMA slows down the blitter.

I wrote a routine on the A1200 which displays 8 lores attached sprites multiplied with the SSCAN2-Bit in FMODE register to get a background display wider than 256 pixels. The copper waits for the blitter copying BOBs and clearing the screen. If I turn off sprite dma, the blitter ends his operations much earlier, when I wait for the last blit to be finished and change the background colour.

[Toni Wilen]

Yes, blitter and CPU can use any free cycle. Neither has odd-only or even-only cycle restriction (like copper).

[dissident]

Originally Posted by Toni Wilen

Yes, blitter and CPU can use any free cycle. Neither has odd-only or even-only cycle restriction (like copper).

Thanks, Toni. This information makes it much clearer as it is documented in the HRM and explains some "strange behaviour" I noticed in conjunction with the blitter and bitplane/sprite-DMA.

[AndNN]

Originally Posted by Toni Wilen

Yes, blitter and CPU can use any free cycle. Neither has odd-only or even-only cycle restriction (like copper).

The time to fire off the blitter is when the scan lines are not processing bit-plane DMA. Also, if you have a fast memory screen and you transfer to chip memory you get speed improvements when no bit-plane DMA is been used - so detect the last line of the screen and start the copy off. If you run at 25fps you can split the copy into 2 sections and start after the last line.