memory read/write penalty

[Auscoder]

Hey all, I understand there are extra memory access needed to read/write to odd addresses on 68020+ and it’s not possible on 68000/010, but what about for 68020+ with a long word read or write to a 2 byte alignment that is not a 4 byte alignment. Any additional cost for longs at those addresses?

As a side question, for the odd addresses is the penalty 2x access cost?

Thanks!

[a/b]

Yeah, 020+ has to read two consecutive 32-bit data if the address is only 1 or 2 byte aligned (not on a 32-bit boundary).

[Auscoder]

Ok good to know, thanks! Couldn’t find much info except for the odd addresses.

[meynaf]

Not all odd addresses have a penalty. If you access a word that is fully contained inside an aligned long, then it is accessed at full speed. IOW, if the word is at an address of 1 modulo 4.

[PeterK]

But what happens when you read word or long sequences from a not aligned memory block? Do you get a possible penalty only for the first read access, but then the following reads can re-use the previous data from the cache and only need to fetch the subsequent words or longwords from memory? Or is there still a cache read penalty?

[paraj]

Originally Posted by PeterK

But what happens when you read word or long sequences from a not aligned memory block? Do you get a possible penalty only for the first read access, but then the following reads can re-use the previous data from the cache and only need to fetch the subsequent words or longwords from memory? Or is there still a cache read penalty?

Cache lookups are performed on a (aligned) longword basis, so if your read operation straddles a longword boundary you'll have 2 cache lookups (each of which could result in a cache miss). Even if both longwords are in the same cache line you'll still occur a penalty. For 68060 it's 1 clock cycle (2 for RMW instructions), see MC68060UM 10.2.5. I'm not sure what the exact penalties are for 030 and 040 but the user manuals contain similar language.

[PeterK]

Thanks paraj, good to know that, because I always have my difficulties to understand the timing tables and the exact calculation of required clock cycles, and under WinUAE I can hardly measure with benchmarks how fast a real CPU would execute the code.