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Old 04 July 2020, 12:47   #21
robinsonb5
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Really nice work!

Quote:
Originally Posted by RemoteFlyer View Post
I'm looking at the differences in processors, and how cache works. I'm working to implement cache on the chip ram. My design only has cache on the fast ram right now.
Be careful with caching chip ram - various processes inside the Amiga (Blitter, disk IO) can write to it in a way that's not visible on the CPU bus, so you can easily end up with stale data in the cache. A better idea for speeding up Chip RAM access might be to implement a write queue, so the CPU doesn't have to wait for writes to complete before continuing.

You should be able to double your SysInfo score without too much trouble.
If you're not already doing so, look at getting your SDRAM controller and cache running in burst mode.

The various Minimig cores run the TG68 and SDRAM at about 113MHz, with the CPU's clkena signal only asserted for one cycle in 8 - though I have had it working with the CPU running 1 cycle in 5 at that speed.

Another approach is to run the CPU on a slower clock and run the SDRAM controller and cache at twice or four times the speed of the CPU. (If you generate the clocks within the same PLL and they're integer multiples of each other you don't have to worry about crossing clock domains - they'll be edge aligned.)

Again, nice work - I look forward to seeing the project's progress!
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Old 04 July 2020, 13:45   #22
RemoteFlyer
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Quote:
Originally Posted by robinsonb5 View Post
Really nice work!...
Thank you, that's all really helpful. The internal dma etc is why I hadn't implemented the chip cache, I'll focus on the write buffer instead. cheers.
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Old 09 July 2020, 15:18   #23
talybont
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There was mention of another core on a different thread: http://eab.abime.net/showpost.php?p=...&postcount=324

Just thought I'd bring attention to it here also, since this is also an FPGA based accelerator.
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Old 09 July 2020, 15:45   #24
AJCopland
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Quote:
Originally Posted by RemoteFlyer View Post
Well it's been a lesson in FPGA design and a great distraction during the lockdown. A working a1200 accelerator with 24MB ram based around the DE0-nano FPGA board. [ Show youtube player ]
Well holy sh*t that's awesome work!
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Old 11 July 2020, 13:00   #25
AJCopland
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@RemoteFlyer I guess I have two questions because I have a DE0-nano lying about from an old project already so:
1) will you be releasing the design of the adapter board so people can build it themselves? (I even have the A1200 connectors)
2) will you be releasing/making available the cpu core?
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