A500 trapdoor memory: free design

[Jope]

Originally Posted by PeteAU

Perfect thanks. I hope I'm not breaking some forum rule by selling a few boards (?)

Feel free, others have done so in the past. :-)

[PeteAU]

Some people ask about a BOM or parts list, so roughly it is:

* Lots of 100nF 0805 X7R capacitors.

For 512K:
* 1 x 1Mx16bit SOJ42 DRAM
* 1 x 56pin (2x28) 2.54mm double row right-angle header (or 2x40pin and cut it)

For A500+ 1MB:
* one more DRAM

For Gary Adapter:
* more DRAMs (any number you want)
* 1 x 74F139 or 74HCT139 (surface mount)
* 3 x 74F00 (surface mount)
* 1 x 74F74 (surface mount)
* 3 x 3-pin jumper headers
* 3 x jumpers
* 2 x 24-pin DIP sockets
* 2 x round pin strips
* Wires and some 2 and 3-pin 2.54mm connectors of your choice (see my photos from previous page).

For the RTC clock:
* See post #14 on page 1.

[PeteAU]

I made a miniaturised variant, with 1 MB and RTC, only 38mm wide But this one's a for-sale, finished product instead. Blatant ad: http://pibus.info/amiga/pa501/

But I've still got a few of the full-size boards if you want to DIY on the cheap. Even a SOJ40 variant, if you prefer that memory type.

[Zippy Zapp]

Very cool. I like the mini variant. Nice work!

[Mathesar]

My boards arrived yesterday! I also got a good deal on our local ebay (marktplaats) for some SIMM sticks so I am ready for some soldering.

However I am a bit puzzled about all the different jumper settings and configurations:

• First of all, I got a rev B board + Gary adapter. It has room for 4 RAM chips. However, the schematics (Eagle files) on your website are for rev A I guess as the schematics show only 3 RAM chips.
• Second, ideally I want to expand my rev 5 A500 to 1MB chip (by modding the mainboard and replacing Agnus) and 1,5MB slow. This is possible right? How do I need to set all the jumpers then? The rev B schematics would be helpful in that respect so I can maybe figure it out on my own.

The PCB looks very nice BTW and I am looking forward to building this nice little expansion
Nice work

[PeteAU]

Originally Posted by Mathesar

My boards arrived yesterday! I also got a good deal on our local ebay (marktplaats) for some SIMM sticks so I am ready for some soldering.

However I am a bit puzzled about all the different jumper settings and configurations:

• First of all, I got a rev B board + Gary adapter. It has room for 4 RAM chips. However, the schematics (Eagle files) on your website are for rev A I guess as the schematics show only 3 RAM chips.
• Second, ideally I want to expand my rev 5 A500 to 1MB chip (by modding the mainboard and replacing Agnus) and 1,5MB slow. This is possible right? How do I need to set all the jumpers then? The rev B schematics would be helpful in that respect so I can maybe figure it out on my own.

The PCB looks very nice BTW and I am looking forward to building this nice little expansion
Nice work

OK I just placed the B2 revision on the first page, 2nd post.

Yeah you can do 1MB Chip + 1.5 Slow if you have a 8372 Agnus.
You can just copy my jumpers from the photos on page 3: http://eab.abime.net/showpost.php?p=...1&postcount=53 . All the RAS need to go to RAS1. Jumpers on the GARY adapter to bottom.

But I would start with a basic 512K expansion first and make sure it works.

[Mathesar]

Originally Posted by PeteAU

OK I just placed the B2 revision on the first page, 2nd post.

Yeah you can do 1MB Chip + 1.5 Slow if you have a 8372 Agnus.
You can just copy my jumpers from the photos on page 3: http://eab.abime.net/showpost.php?p=...1&postcount=53 . All the RAS need to go to RAS1. Jumpers on the GARY adapter to bottom.

But I would start with a basic 512K expansion first and make sure it works.

Thanks!

I will take up your advice to start with a basic 512K expansion first.
I intend to fully utilize this little design (including the RTC) to be able to run WHDload on the A500. I'll keep you posted!

[Mathesar]

Today I seperated the trapdoor PCB and the Gary PCB.
I also soldered the RAM chips and the decoupling capacitors on the board.
I couldn't resist soldering all the RAM chip even though I will try a plain 512K expansion first.

The soldering went really well but you do need a very small soldering tip to get between the legs of the SOJ42 chips and the board. Luckily the pads are not too short.

I am still waiting for the other parts. They will probably come in Tuesday or so.

I'll keep you posted!

[PeteAU]

Originally Posted by Mathesar

Today I seperated the trapdoor PCB and the Gary PCB.
I also soldered the RAM chips and the decoupling capacitors on the board.
I couldn't resist soldering all the RAM chip even though I will try a plain 512K expansion first.

The soldering went really well but you do need a very small soldering tip to get between the legs of the SOJ42 chips and the board. Luckily the pads are not too short.

I am still waiting for the other parts. They will probably come in Tuesday or so.

I'll keep you posted!

German memory . I guess it should work with WHDload, I never thought about it. It just needs 2MB+ right?

[Mathesar]

Originally Posted by PeteAU

German memory . I guess it should work with WHDload, I never thought about it. It just needs 2MB+ right?

I could choose between Hynix, Samsung and Siemens. I went for german engineering . I hope they survived the desoldering process....

WHDload ideally needs some more RAM but 2,5MB should get a lot of games going I hope. Next step for my 500 is a kickstart upgrade and a DIY harddisk controller.

BTW, some components came in today and I have now soldered the Gary adapter.

[Mathesar]

Just a quick update:

The board and Gary adapter are working! I still have to do the 1MB agnus mod so I still have only 512KB chip. But I do have 1,5MB Slow!!!! Yeah
The RTC is also working. It keeps its time when I power off the computer. Even the little red LED on the bottom works
BTW, I used a 74HCT139 as I couldn't easily source an 74F139. I think HCT is a little bit faster than LS and it seems to work fine.

Next step is to clean up the wiring and do the 1MB Agnus mod. I will post some pictures then.

Well done Pete

[Mathesar]

As promised a picture from my build.

The build went pretty smooth but it would be helpfull if there was a table/guide somewhere with all the jumper settings. Some details (like having to cut the default trace on the JP2 motherboard jumper) weren't immediately clear to me. Also a small comment on the PCB: the holes for the jumper pins seem slightly to small. I had some gold-plated pin headers laying around that wouldn't fit.

Other than that I'm pretty happy. This miggy now got 5 times as much memory as when she left the factory

[PeteAU]

Originally Posted by Mathesar

As promised a picture from my build.

The build went pretty smooth but it would be helpfull if there was a table/guide somewhere with all the jumper settings. Some details (like having to cut the default trace on the JP2 motherboard jumper) weren't immediately clear to me. Also a small comment on the PCB: the holes for the jumper pins seem slightly to small. I had some gold-plated pin headers laying around that wouldn't fit.

Other than that I'm pretty happy. This miggy now got 5 times as much memory as when she left the factory

Good job. Which RTC chip is that? ... Now add plasmab's accelerator

What's with the silk screen missing from the gary board, it washed off?

[Mathesar]

Originally Posted by PeteAU

Good job. Which RTC chip is that? ... Now add plasmab's accelerator

What's with the silk screen missing from the gary board, it washed off?

The RTC chip is an RTC-62421A. It doesn't need a crystal so that is easy.
The silk screen is OK. It just didn't come through on the photo.

Yeah, PlasmaB's 030 accelerator is starting to look very nice indeed. In fact, his project prompted me to buy this A500...

[Mathesar]

Has anyone used the Gary adapter to have 1meg chipram ?

I have discovered a bug which corrupts memory if you use the Gary adapter with a 1meg Agnus to increase chipram.

The problem is with Agnus DMA cycles. If Agnus wants to access the chipram it asserts either RAS0 or RAS1. RAS0 selects the internal 512K bank (@ $000000), RAS1 selects the external trapdoor 512K bank (@ $080000). With the Gary adapter installed RAS1 selects one of the 4 RAM chips (U1..U4) depending on the state of the CPU address bus. However, during a DMA cycle, Agnus expects to access U1 ($080000) which might not be the case if the CPU bus is selecting another RAM bank!

To fix this the Gary adapter needs to make sure U1 is always select during an Agnus DMA cycle. I have designed a little circuit that is currently living on a piece of veroboard that does this. See attached pictures and logic analyzer traces. The circuit works as follows:
When Agnus is going to do an internal cycle it announces this to Gary by asserting _blit. As _blit is not asserted long enough to set the sel[1:0] lines to 0 during a complete _CAS cycle, the flipflops are added. The flipflops are clocked on the rising edge off CCKQ and they make sure the sel[1:0] are stable during an entire _CAS cycle. You can clearly see the effect on the analyzer traces. It can be seen that the CPU bus indeed sometimes selects the wrong RAM bank during an internal Agnus cycle.

I am now designing a new Gary adapter that includes the extra circuitry and I will post the design here. Note that the bug only affects extra Chipram on a normal A500 that was upgraded with a 1meg Agnus.

If you only use the trapdoor board + gary adapter to get some extra slowram there is no problem.

[PeteAU]

Originally Posted by Mathesar

Has anyone used the Gary adapter to have 1meg chipram ?

Maybe nobody, I think people mostly used it as 512K or 1024K (A500+).

Originally Posted by Mathesar

I have discovered a bug which corrupts memory if you use the Gary adapter with a 1meg Agnus to increase chipram.

The problem is with Agnus DMA cycles. If Agnus wants to access the chipram it asserts either RAS0 or RAS1. RAS0 selects the internal 512K bank (@ $000000), RAS1 selects the external trapdoor 512K bank (@ $080000). With the Gary adapter installed RAS1 selects one of the 4 RAM chips (U1..U4) depending on the state of the CPU address bus. However, during a DMA cycle, Agnus expects to access U1 ($080000) which might not be the case if the CPU bus is selecting another RAM bank!

To fix this the Gary adapter needs to make sure U1 is always select during an Agnus DMA cycle. I have designed a little circuit that is currently living on a piece of veroboard that does this. See attached pictures and logic analyzer traces. The circuit works as follows:
When Agnus is going to do an internal cycle it announces this to Gary by asserting _blit. As _blit is not asserted long enough to set the sel[1:0] lines to 0 during a complete _CAS cycle, the flipflops are added. The flipflops are clocked on the rising edge off CCKQ and they make sure the sel[1:0] are stable during an entire _CAS cycle. You can clearly see the effect on the analyzer traces. It can be seen that the CPU bus indeed sometimes selects the wrong RAM bank during an internal Agnus cycle.

I am now designing a new Gary adapter that includes the extra circuitry and I will post the design here. Note that the bug only affects extra Chipram on a normal A500 that was upgraded with a 1meg Agnus.

If you only use the trapdoor board + gary adapter to get some extra slowram there is no problem.

Go ahead and re-spin the gary board, that's why it's open source.
Aren't you tempted to do the whole job in the smallest CPLD you can find? Or a GAL16v8 for nostalgia?

[obitus1990]

Originally Posted by PeteAU

I made a miniaturised variant, with 1 MB and RTC, only 38mm wide But this one's a for-sale, finished product instead. Blatant ad: http://pibus.info/amiga/pa501/



But I've still got a few of the full-size boards if you want to DIY on the cheap. Even a SOJ40 variant, if you prefer that memory type.

Having purchased one of these myself, it's very nicely done. And the silkscreen of the B52 was an added touch.

[Mathesar]

Originally Posted by PeteAU

Maybe nobody, I think people mostly used it as 512K or 1024K (A500+).



Go ahead and re-spin the gary board, that's why it's open source.
Aren't you tempted to do the whole job in the smallest CPLD you can find? Or a GAL16v8 for nostalgia?

Hi,

I send you a PM but I guess it didn't arrive. Yes, I will respin the board. I finished the schematic and I hope to do the routing this weekend. Are you interested in a new Gary board as well? (As you have also upgraded to a fatter Agnus?)

I will stick to SMD 74F or 74HCT logic. The nice thing about TTL is that you don't need a programmer so people can easily build it.

So I guess you and I are the only one with all the bells and whistles enabled huh? Ah well, it was a fun project finding out what was wrong with it. I could finally use my el-cheapo ebay logic analyzer.

[Mathesar]

I have send of the Gerbers for the new Gary adapter to the PCB manufacturer (Elecrow).
Should take about 3 weeks or so to come in. Fingers crossed that I didn't make a mistake .

I will have some spares left so if anyone is interested in one please drop me a PM.

[PeteAU]

Originally Posted by Mathesar

I have send of the Gerbers for the new Gary adapter to the PCB manufacturer (Elecrow).
Should take about 3 weeks or so to come in. Fingers crossed that I didn't make a mistake .

I will have some spares left so if anyone is interested in one please drop me a PM.

Neat Looks familiar but slightly different.

Are the SO14's pads long enough? I guess they'll squeeze on.
I found I needed to space the gary/mobo holes a certain distance to make DIP24 sockets fit, but it looks like machined pin strips will be the way to go with yours.

I'll wait to see you populate one before asking you for a board