21 January 2022, 01:32 | #21 |
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One possible way to gain more color register writes is to wait for $ce and modify the pointers for bitplane 4 before the others.
Should be able to get 14 colors changed. |
21 January 2022, 01:43 | #22 | |
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I would use the copper for *at least* 2 reasons: - there is no possibility to execute the writing routine with the CPU if the blitter is active and in nasty mode (target seems OCS/Chip or bogus RAM machines), the copper is the only one who can pause it by temporarily disabling its DMA (in any case I would do it even without nasty active, the blitter could steal too many cycles if in a crowded area with other DMA); - somehow you have to initialize an entry point through an IRQ, if possible of a high level and in a position of the beam that is sufficiently early to also make up for the execution of a possible instruction in progress that requires many cycles (and only the copper can do it properly, there is another problem related to the possible simultaneous use of IRQ6, but the solution is not trivial and I will not discuss it here). It is therefore not easy to carry out this pair of movem without struggle and for sure the copper is of great help |
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21 January 2022, 04:19 | #23 | |
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21 January 2022, 09:14 | #24 | |
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What CIAB level 6 interrupt do is use hsync to decrease the prescaler and trigger IRQ on underflow. So you need the pre-sync the counter to a defined position, and anyway hope that the line start time is right for all the necessary initializations (you basically need a post sync during the Level 6 IRQ). No one on the Amiga uses CIAB to synchronize line by line basis for a reason, it is used for timed events. And we are completely excluding the case of another IRQ6 arriving at the same time... There's a reason why I said it was crazy, for such a case at least. However I have seen code that does much crazier things |
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21 January 2022, 13:27 | #25 |
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I love all these alternate ideas for something seemingly so simple.
But nobody has suggested using the blitter to set a bunch of color registers. Is that possible? How fast would it be with nasty set? |
21 January 2022, 14:15 | #26 |
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I looked it up and dff000 is not in chip ram. I guessed as much but couldn’t remember. What a pity. That would have been fun!
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21 January 2022, 15:02 | #27 | |
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Another interesting modality it could have been copper with an extra instruction (and it wouldn't have been difficult to implement either): CMOVEM Some bits in the upper part of the first fetch could have been used as encoding space, as a counter. In an alternate universe |
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21 January 2022, 15:09 | #28 | |
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Same alternative universe could also have a CMOVER (repeatedly move values from the list after the CMOVER to the same register over and over). Ah well, the Copper is still great even with it's quirks |
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21 January 2022, 15:27 | #29 |
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21 January 2022, 18:32 | #30 |
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While we are still in fantasy land, 68000 with index scaling :P.
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