02 February 2023, 15:33 | #101 |
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Could the large Phase5 version of the 68040.library be based on Commodore's version, expanded with (a lot of) their own code?
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03 February 2023, 10:11 | #102 | |
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Location: Germany
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Quote:
What is certain is that it contains both the motorola FPSP and ISP code, (as in every 68040.library), but it also contains the code to drive the MMU (which is a separate library in my setup that is shared between CPU models). It also contains a lot of vendor specific stuff "who knows what". In my operation model, this P5 vendor part is part of the "p5emu.library" which is created by the "P5Init" tool. This tool is not very large in my case, but I do not exactly know how complete my emulation is. But there is certainly more in it, to drive the interface towards PPC if there is one. Nobody knows how that works, it is undocumented. I don't support the PPCs. |
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10 March 2023, 01:56 | #103 |
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This was something I observed with the RSCP benchmark - in some cases.
There's a fairly hires screen brought up for the benchmark (interlace) and I have watched this interlace screen jiggle up and down one line every so often on some setups during the data reads targeting ChipRAM. I don't see it with <~1.5MB/sec stuff. It was higher-end SCSI performance devices usually. I know I see on occasion with DMA controllers, and that amounts to the the A2091/A590, GVP Series II interfaces, and the Microbotics HardFrame. I have several of the two former cards. There are others (older) like the Supra and the A2090 in existence, but I shudder if anyone uses them anymore. Anyway - as noted, I assume it's heavy DMA to ChipRAM that is triggering things, but that's all I know. Last edited by thebajaguy; 10 March 2023 at 02:10. |
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