MMUlib support / explanation wanted

spudje · 28 March 2020, 12:14

So, I took some time to study all the MMUlib documentation. But honestly nothing in the documentation really explained how a correct config should look, so I have no clue how to judge the configs. Still I took the jump to install it on my A4000D. Specs of the system:

A4000D
16MB Fast RAM, 2 MB Chip Ram
3.1.4 ROMs
CSPPC & 128 MB
Mediator (3V)
BigRAM+ 256 MB
Highway USB
Voodoo 3 (16 MB)
SB128
rtl8029 NIC
AOS 3.1.4.1

1. So I installed MMUlib, first just with the installer.
I said no to the P5 accelerator question. As the documentation is unclear IMO. Reading it multiple times I understand you only need the P5 patch for blizzards not for cyberstorms.

Muscan output:

Code:

MuScan 46.1 (02.07.2016) © THOR

68060 MMU detected.
MMU page size is 0x1000 bytes.

Memory map:
0x00000000 - 0x001FFFFF CacheInhibit Imprecise NonSerial 
0x00200000 - 0x00BBFFFF Blank 
0x00BC0000 - 0x00BFFFFF CacheInhibit I/O space 
0x00C00000 - 0x00D7FFFF Blank 
0x00D80000 - 0x00DFFFFF CacheInhibit I/O space 
0x00E00000 - 0x00E8FFFF Blank 
0x00E90000 - 0x00E9FFFF CacheInhibit I/O space 
0x00EA0000 - 0x00EFFFFF Blank 
0x00F00000 - 0x00F00FFF CacheInhibit 
0x00F01000 - 0x00F21FFF CacheInhibit I/O space 
0x00F22000 - 0x00F7FFFF CacheInhibit 
0x00F80000 - 0x00FFFFFF ROM 
0x01000000 - 0x06FFFFFF Blank 
0x07000000 - 0x0FF7FFFF CopyBack 
0x0FF80000 - 0x3FFFFFFF Blank 
0x40000000 - 0x50FFFFFF CacheInhibit I/O space 
0x51000000 - 0x5FFFFFFF Blank 
0x60000000 - 0x6FFFFFFF CopyBack 
0x70000000 - 0xFFFFFFFF Blank

Config:

Code:

;*************************************************************************
;** MMU Configuration file						**	
;**									**
;** this file is read on startup by the mmu.library and used to modify	**
;** the pre-calculated or scanned MMU table				**
;**									**
;** © 1999-2018 THOR Software, Thomas Richter				**
;*************************************************************************


; the current version of the MMU library knows six commands that can
; be used in this file: 
; CLEARTTX clears all or parts of the transparent translation registers
; ADDMEM   adds memory to the exec free list pool. BE WARNED, this command
;	   does NOT modify the MMU tables, this must be done by yourself
; SETCACHEMODE	defines the MMU tables.
; DESCRIPTORCACHEINHIBIT defines whether the data cache should be disabled
;          for the MMU descriptors. It's usually OFF meaning the cache will 
;	   remain enabled. This is fine for the mmu.library, but certain 
;	   hacks might require a ON argument here. Note that this means more 
;	   work for the library.
; FOR	   executes a command only for a specific hardware expansion which is
;	   given by the manufacturer and product ID.
; CLEARMMU overrides the MMU configuration found by the library for selected
;	   parts of the configuration.
;
; All other commands are currently "external". The library will scan for
; these commands in "LIBS:mmu" and execute them on startup. These *are not*
; standard shell commands. They cannot be run from the shell, and shell
; commands cannot be started from this file.
;


ClearTTx	;ignore all TTX registers if any. We don't need them.
		;this will speed up the system for some machines.

ClearMMU Memory Blank Motherboard
		;re-initialize some resources 


; Remove the semicolon in the line below if you have to live with other MMU
; hacks that expect the MMU descriptors in non-cacheable memory. This is by
; default OFF, i.e. descriptors will be cachable.
; The library will work fine and will take all precautions for descriptors
; in the cache, but some third-party hacks might not.

;DescriptorCacheInhibit ON


; Remove the semicolon in the two lines below in case you encounter hangs or
; crashes with Zorro-II 16-Bit memory. It will disable caching for the Z-II
; area. Clearly, this is slower, but it will work, at least.

;SetCacheMode from 0x00200000 size 0x00800000 CacheInhibit NonSerial Imprecise
;ClearMMU Expansion

; The following lines are strictly speaking not necessary.
; They will change and optimize the caching mode for graphics boards,
; but it will also work without them.
;
; The Picasso96 software will also optimize the MMU caching mode itself
; and therefore makes the following completely superfluous. 
; CyberGraphics does not take these steps and might profit from the
; following.
;
; To speedup booting, you may remove all the lines of the boards 
; you do not own.
;


; Altais
For 18260 19	SetCacheMode {base}		{size}		CacheInhibit NonSerial Imprecise

;Retina Z3
For 18260 16 Z3	SetCacheMode {base+0x00c00000}	0x00400000	CacheInhibit NonSerial Imprecise

;Merlin
For 2117 3 Z3	SetCacheMode {base+0x00c00000}	0x00400000	CacheInhibit NonSerial Imprecise
For 2117 3 Z2	SetCacheMode {base}		{size}		CacheInhibit NonSerial Imprecise

;oMniBus, Size > 0x00100000
For 2181 0 BIG	SetCacheMode {base+0x00c00000}	0x00200000	CacheInhibit NonSerial Imprecise

;Graffity Z2
For 2092 33 Z2	SetCacheMode {base}		{size}		CacheInhibit NonSerial Imprecise

;Graffity Z3
For 2092 33 Z3	SetCacheMode {base+0x00c00000}	0x00200000	CacheInhibit NonSerial Imprecise

;Domino
For 2167 1 Z2	SetCacheMode {base}		{size}		CacheInhibit NonSerial Imprecise

;PicassoII
For 2167 11	SetCacheMode {base}		{size}		CacheInhibit NonSerial Imprecise

;GVP Spectrum
For 2193 1	SetCacheMode {base}		{size}		CacheInhibit NonSerial Imprecise

;Piccolo
For 2195 5	SetCacheMode {base}		{size}		CacheInhibit NonSerial Imprecise

;Piccolo-SD64 Z2
For 2195 10 Z2	SetCacheMode {base}		{size}		CacheInhibit NonSerial Imprecise

;Piccolo-SD64 Z3
For 2195 10 Z3	SetCacheMode {base}		0x00400000	CacheInhibit NonSerial Imprecise

;VA2000
For 28014 1 	SetCacheMode {base}		0x10000		Valid CacheInhibit IOSpace
For 28014 1 	SetCacheMode {base+0x10000}	{size-0x10000}	Valid CacheInhibit NonSerial Imprecise

;Cybervision Z3
For 8512 34 Z3	SetCacheMode {base}		{size} 		Blank IOSpace
For 8512 34 Z3	SetCacheMode {base}		0x01400000	Valid IOSpace CacheInhibit
For 8512 34 Z3	SetCacheMode {base+0x01400000}	0x00c00000	Valid IOSpace CacheInhibit NonSerial Imprecise
For 8512 34 Z3	SetCacheMode {base+0x02000000}	0x02000000	Valid IOSpace CacheInhibit

;CyberVision 3D
For 8512 67	SetCacheMode {base} 		{size}		Blank IOSpace
For 8512 67 Z2	SetCacheMode {base}		0x00380000	Valid IOSpace CacheInhibit NonSerial Imprecise
For 8512 67 Z2	SetCacheMode {base+0x00380000}	0x00080000	Valid IOSpace CacheInhibit
For 8512 67 Z3	SetCacheMode {base+0x04000000}	0x01000000	Valid IOSpace CacheInhibit NonSerial Imprecise
For 8512 67 Z3	SetCacheMode {base+0x05000000}	0x00010000	Valid IOSpace CacheInhibit
For 8512 67 Z3	SetCacheMode {base+0x05800000}	0x00008000	Valid IOSpace CacheInhibit
For 8512 67 Z3	SetCacheMode {base+0x07000000}	0x00008000	Valid IOSpace CacheInhibit
For 8512 67 Z3	SetCacheMode {base+0x08000000}	0x00001000	Valid IOSpace CacheInhibit
For 8512 67 Z3	SetCacheMode {base+0x0c000000}	0x00010000	Valid IOSpace CacheInhibit
For 8512 67 Z3	SetCacheMode {base+0x0c0e0000}	0x00001000	Valid IOSpace CacheInhibit

;Rainbow III
For 2145 33	SetCacheMode {base}		{size}		Blank IOSpace
For 2145 33	SetCacheMode {base}		0x00400000	Valid IOSpace CacheInhibit

;MK-III SCSI Hostadapter
For 8512 100	SetCacheMode {base}		{size}		Valid IOSpace CacheInhibit

;Blizzard PPC SCSI Hostadapter
For 8512 110	SetCacheMode {base}		{size}		Valid IOSpace CacheInhibit

;
; The following define areas for the CBM bridgeboards. These boards
; actually do not need the caching mode setup indicated below, but
; the buggy 32.xx and 33.xx janus.library and tools will.
; Therefore, remove the comments below if you *must* run these buggy
; versions.
;

;A2088 Bridgeboard
;For 513 1	SetCacheMode 0x00e00000 	0x00180000	Valid IoSpace CacheInhibit

;A2286 Bridgeboard
;For 513 2	SetCacheMode 0x00e00000 	0x00180000	Valid IoSpace CacheInhibit

;A2386 Bridgeboard
;For 513 103	SetCacheMode 0x00e00000		0x00180000	Valid IoSpace CacheInhibit

; that's all folks!

2. Then I ran BuildMMUConfig.rexx

Muscan result:

Code:

MuScan 46.1 (02.07.2016) © THOR

68060 MMU detected.
MMU page size is 0x1000 bytes.

Memory map:
0x00000000 - 0x001FFFFF CacheInhibit Imprecise NonSerial 
0x00200000 - 0x00BBFFFF Blank 
0x00BC0000 - 0x00BFFFFF CacheInhibit I/O space 
0x00C00000 - 0x00D7FFFF Blank 
0x00D80000 - 0x00DFFFFF CacheInhibit I/O space 
0x00E00000 - 0x00E8FFFF Blank 
0x00E90000 - 0x00E9FFFF CacheInhibit I/O space 
0x00EA0000 - 0x00EFFFFF Blank 
0x00F00000 - 0x00F00FFF CacheInhibit 
0x00F01000 - 0x00F21FFF CacheInhibit I/O space 
0x00F22000 - 0x00F7FFFF CacheInhibit 
0x00F80000 - 0x00FFFFFF CopyBack 
0x01000000 - 0x06FFFFFF Blank 
0x07000000 - 0x08026FFF CopyBack 
0x08027000 - 0x08029FFF CacheInhibit 
0x0802A000 - 0x0FF7FFFF CopyBack 
0x0FF80000 - 0x0FFFFFFF CacheInhibit 
0x10000000 - 0x3FFFFFFF Blank 
0x40000000 - 0x50FFFFFF CacheInhibit I/O space 
0x51000000 - 0x5FFFFFFF Blank 
0x60000000 - 0x6FFFFFFF CopyBack 
0x70000000 - 0xFFEFFFFF Blank 
0xFFF00000 - 0xFFF7FFFF CacheInhibit 
0xFFF80000 - 0xFFFFFFFF Blank

Config, as you see, the script enabled the P5 patch.

Code:

;*************************************************************************
;** MMU Configuration file                                              **
;**                                                                     **
;** this file is read on startup by the mmu.library and used to modify  **
;** the pre-calculated or scanned MMU table                             **
;**                                                                     **
;** © 1999-2018 THOR Software, Thomas Richter                           **
;*************************************************************************



; the current version of the MMU library knows four commands that can
; be used in this file:
; CLEARTTX clears all or parts of the transparent translation registers
; ADDMEM   adds memory to the exec free list pool. BE WARNED, this command
;          does NOT modify the MMU tables, this must be done manually with
;          SETCACHEMODE
; SETCACHEMODE  defines the MMU tables.
; DESCRIPTORCACHEINHIBIT defines whether the data cache should be disabled
; for the MMU descriptors. It's usually OFF meaning the cache will remain
; enabled. This is fine for the mmu.library, but certain hacks might require
; an ON argument here. Note that this means more work for the library.


ClearTTx        ;ignore all TTX registers if any. We don't need them

;DescriptorCacheInhibit ON	;make access to MMU descriptors cache inhibited


;Board specific setup follows here,
;generated by BuildMMUConfig 1.10 © 29.07.2000 THOR-Software

;General memory setup follows.
;The following lines are a compatibility kludge for some P5 boards
;which enable the MMU prior to the 68040/68060 library and leave
;the memory in CACHEINHIBIT state. You may remove the following
;lines on all other machines most likely.

SetCacheMode from 0x07000000 size 0x08F80000 Copyback
SetCacheMode from 0x60000000 size 0x10000000 Copyback
SetCacheMode from 0x00000000 size 0x00200000 CacheInhibit NonSerial Imprecise

;Memory setup end.


;Setup for board 2206/161

;Setup for board 2206/33

;Setup for board 3643/32
;This board contains memory and requires no special threadment.
;In case accessing this memory with COPYBACK enabled causes crashes,
;please remove the semicolon in front of the next line:
;SetCacheMode FROM 0x60000000 SIZE 0x10000000 CACHEINHIBIT NONSERIAL IMPRECISE

;Setup for board 2145/200

;Setup for board 8512/100
;MK-III SCSI Hostadapter
For 8512 100 SetCacheMode FROM {base} SIZE {size} VALID IOSPACE CACHEINHIBIT


;P5 fixes follow here:
;If you do not own a P5 board, you may remove the following lines
;
;Several P5 boards build a private MMU setup on boot
;using a kludge called the BOOT-MMU-Port. To run this
;kludge, the following external command is run from
;LIBS:mmu/ as all other external commands
;
;This command installs also other P5 relevant MMU settings
;Hence, for P5 boards, please keep it in place even if
;you *DO NOT* see the BOOT-MMU-Port.
;
P5Init

continued in next post.

spudje · 28 March 2020, 12:14

3. Then I tried the other script, ScanToConfig.rexx, and did not yet edit the config, again including P5init.

Muscan:

Code:

MuScan 46.1 (02.07.2016) © THOR

68060 MMU detected.
MMU page size is 0x1000 bytes.

Memory map:
0x00000000 - 0x001FFFFF CacheInhibit Imprecise NonSerial 
0x00200000 - 0x00BBFFFF Blank 
0x00BC0000 - 0x00BFFFFF CacheInhibit I/O space 
0x00C00000 - 0x00D7FFFF Blank 
0x00D80000 - 0x00DFFFFF CacheInhibit I/O space 
0x00E00000 - 0x00E8FFFF Blank 
0x00E90000 - 0x00E9FFFF CacheInhibit I/O space 
0x00EA0000 - 0x00EFFFFF Blank 
0x00F00000 - 0x00F00FFF CacheInhibit 
0x00F01000 - 0x00F21FFF CacheInhibit I/O space 
0x00F22000 - 0x00F4FFFF CacheInhibit 
0x00F50000 - 0x00F5FFFF CacheInhibit I/O space 
0x00F60000 - 0x00F7FFFF CacheInhibit 
0x00F80000 - 0x00FFFFFF CopyBack 
0x01000000 - 0x06FFFFFF Blank 
0x07000000 - 0x08026FFF CopyBack 
0x08027000 - 0x08029FFF CacheInhibit 
0x0802A000 - 0x0FF7FFFF CopyBack 
0x0FF80000 - 0x0FFFFFFF CacheInhibit 
0x10000000 - 0x3FFFFFFF Blank 
0x40000000 - 0x50FFFFFF CacheInhibit I/O space 
0x51000000 - 0x5FFFFFFF Blank 
0x60000000 - 0x6FFFFFFF CopyBack I/O space 
0x70000000 - 0xFFEFFFFF Blank 
0xFFF00000 - 0xFFF7FFFF CacheInhibit 
0xFFF80000 - 0xFFFFFFFF Blank

Config:

Code:

;*************************************************************************
;** MMU Configuration file                                              **
;**                                                                     **
;** this file is read on startup by the mmu.library and used to modify  **
;** the pre-calculated or scanned MMU table                             **
;**                                                                     **
;** © 1999,2000 THOR Software, Thomas Richter                           **
;*************************************************************************



; the current version of the MMU library knows four commands that can
; be used in this file:
; CLEARTTX clears all or parts of the transparent translation registers
; ADDMEM   adds memory to the exec free list pool. BE WARNED, this command
;          does NOT modify the MMU tables, this must be done manually with
;          SETCACHEMODE
; SETCACHEMODE  defines the MMU tables.
; DESCRIPTORCACHEINHIBIT defines whether the data cache should be disabled
; for the MMU descriptors. It's usually OFF meaning the cache will remain
; enabled. This is fine for the mmu.library, but certain hacks might require
; an ON argument here. Note that this means more work for the library.


ClearTTx        ;ignore all TTX registers if any. We don't need them

;DescriptorCacheInhibit ON     ;make access to MMU descriptors cache inhibited


;Board specific setup follows here,
;generated by ScanToConfig 1.04 © 14.04.2000 THOR-Software

;General memory setup follows.
;The following lines are a compatibility kludge for some P5 boards
;which enable the MMU prior to the 68040/68060 library and leave
;the memory in CACHEINHIBIT state. You may remove the following
;lines on all other machines most likely.

SetCacheMode from 0x07000000 size 0x08F80000 Copyback
SetCacheMode from 0x60000000 size 0x10000000 Copyback
SetCacheMode from 0x00000000 size 0x00200000 CacheInhibit NonSerial Imprecise

;Memory setup end.


;In case you don't run the V40 68040 resp. 68060.library
;the following line will speed up the chip memory. It is
;not required otherwise.
SetCacheMode 0x000 Size 0x200000 CacheInhibit Imprecise NonSerial

SetCacheMode 0xE90000 Size 0x10000 CacheInhibit Valid IOSpace

;The following memory region should be left blank
;according to the CBM design rules. It isn't...
SetCacheMode 0xF00000 Size 0x1000 CacheInhibit Valid IOSpace

SetCacheMode 0xF01000 Size 0x21000 CacheInhibit Valid IOSpace

;The following memory region should be left blank
;according to the CBM design rules. It isn't...
SetCacheMode 0xF22000 Size 0x5E000 CacheInhibit Valid IOSpace

WARNING! Found non-copyback memory regions.
This could mean that either the ppc.library is running
or P5 I/O hardware is active.
For the time being, I do nothing about it, but you could
try to remove the semi-colon for the following lines:
;SetCacheMode 0x1000000 Size 0x6000000 WriteThrough Valid
;SetCacheMode 0x8027000 Size 0x3000 CacheInhibit Valid
;If you don't own a PPC, you may remove the next line:
SetCacheMode 0x8027000 Size 0x3000 CacheInhibit  Valid

;If you don't own a PPC, you may remove the next line:
SetCacheMode 0x802A000 Size 0x7F56000 CopyBack  Valid

;SetCacheMode 0xFF80000 Size 0x80000 CacheInhibit Valid
;If you don't own a PPC, you may remove the next line:
SetCacheMode 0xFF80000 Size 0x80000 CacheInhibit  Valid

SetCacheMode 0x40000000 Size 0x11000000 CacheInhibit Valid IOSpace

;If you don't own a PPC, you may remove the next line:
SetCacheMode 0x40000000 Size 0x11000000 CacheInhibit IOSpace Valid

SetCacheMode 0x60000000 Size 0x10000000 CopyBack Valid IOSpace

;If you don't own a PPC, you may remove the next line:
SetCacheMode 0x60000000 Size 0x10000000 CopyBack IOSpace Valid

;The following memory region should be left blank
;according to the CBM design rules. It isn't...
SetCacheMode 0xFFF00000 Size 0x80000 CacheInhibit Valid IOSpace


;P5 fixes follow here:
;If you do not own a P5 board, you may remove the following lines
;
;Several P5 boards build a private MMU setup on boot
;using a kludge called the BOOT-MMU-Port. To run this
;kludge, the following external command is run from
;LIBS:mmu/ as all other external commands
;
;This command installs also other P5 relevant MMU settings
;Hence, for P5 boards, please keep it in place even if
;you *DO NOT* see the BOOT-MMU-Port.
;
P5Init

4. Finally I edited the config, according to the PPC guidelines in the config file. I tried with both P5 init enabled and disabled, but didn't notice much difference. below is the info with P5 enabled.

Code:

MuScan 46.1 (02.07.2016) © THOR

68060 MMU detected.
MMU page size is 0x1000 bytes.

Memory map:
0x00000000 - 0x001FFFFF CacheInhibit Imprecise NonSerial 
0x00200000 - 0x00BBFFFF Blank 
0x00BC0000 - 0x00BFFFFF CacheInhibit I/O space 
0x00C00000 - 0x00D7FFFF Blank 
0x00D80000 - 0x00DFFFFF CacheInhibit I/O space 
0x00E00000 - 0x00E8FFFF Blank 
0x00E90000 - 0x00E9FFFF CacheInhibit I/O space 
0x00EA0000 - 0x00EFFFFF Blank 
0x00F00000 - 0x00F00FFF CacheInhibit 
0x00F01000 - 0x00F21FFF CacheInhibit I/O space 
0x00F22000 - 0x00F4FFFF CacheInhibit 
0x00F50000 - 0x00F5FFFF CacheInhibit I/O space 
0x00F60000 - 0x00F7FFFF CacheInhibit 
0x00F80000 - 0x00FFFFFF CopyBack 
0x01000000 - 0x06FFFFFF 
0x07000000 - 0x08026FFF CopyBack 
0x08027000 - 0x08029FFF CacheInhibit 
0x0802A000 - 0x0FF7FFFF CopyBack 
0x0FF80000 - 0x0FFFFFFF CacheInhibit 
0x10000000 - 0x3FFFFFFF Blank 
0x40000000 - 0x50FFFFFF CacheInhibit I/O space 
0x51000000 - 0x5FFFFFFF Blank 
0x60000000 - 0x6FFFFFFF CopyBack I/O space 
0x70000000 - 0xFFEFFFFF Blank 
0xFFF00000 - 0xFFF7FFFF CacheInhibit 
0xFFF80000 - 0xFFFFFFFF Blank

Config:

Code:

;*************************************************************************
;** MMU Configuration file                                              **
;**                                                                     **
;** this file is read on startup by the mmu.library and used to modify  **
;** the pre-calculated or scanned MMU table                             **
;**                                                                     **
;** © 1999,2000 THOR Software, Thomas Richter                           **
;*************************************************************************



; the current version of the MMU library knows four commands that can
; be used in this file:
; CLEARTTX clears all or parts of the transparent translation registers
; ADDMEM   adds memory to the exec free list pool. BE WARNED, this command
;          does NOT modify the MMU tables, this must be done manually with
;          SETCACHEMODE
; SETCACHEMODE  defines the MMU tables.
; DESCRIPTORCACHEINHIBIT defines whether the data cache should be disabled
; for the MMU descriptors. It's usually OFF meaning the cache will remain
; enabled. This is fine for the mmu.library, but certain hacks might require
; an ON argument here. Note that this means more work for the library.


ClearTTx        ;ignore all TTX registers if any. We don't need them

;DescriptorCacheInhibit ON     ;make access to MMU descriptors cache inhibited


;Board specific setup follows here,
;generated by ScanToConfig 1.04 © 14.04.2000 THOR-Software

;General memory setup follows.
;The following lines are a compatibility kludge for some P5 boards
;which enable the MMU prior to the 68040/68060 library and leave
;the memory in CACHEINHIBIT state. You may remove the following
;lines on all other machines most likely.

SetCacheMode from 0x07000000 size 0x08F80000 Copyback
SetCacheMode from 0x60000000 size 0x10000000 Copyback
SetCacheMode from 0x00000000 size 0x00200000 CacheInhibit NonSerial Imprecise

;Memory setup end.


;In case you don't run the V40 68040 resp. 68060.library
;the following line will speed up the chip memory. It is
;not required otherwise.
SetCacheMode 0x000 Size 0x200000 CacheInhibit Imprecise NonSerial

SetCacheMode 0xE90000 Size 0x10000 CacheInhibit Valid IOSpace

;The following memory region should be left blank
;according to the CBM design rules. It isn't...
SetCacheMode 0xF00000 Size 0x1000 CacheInhibit Valid IOSpace

SetCacheMode 0xF01000 Size 0x21000 CacheInhibit Valid IOSpace

;The following memory region should be left blank
;according to the CBM design rules. It isn't...
SetCacheMode 0xF22000 Size 0x5E000 CacheInhibit Valid IOSpace

;WARNING! Found non-copyback memory regions.
;This could mean that either the ppc.library is running
;or P5 I/O hardware is active.
;For the time being, I do nothing about it, but you could
;try to remove the semi-colon for the following lines:
SetCacheMode 0x1000000 Size 0x6000000 WriteThrough Valid
SetCacheMode 0x8027000 Size 0x3000 CacheInhibit Valid
;If you don't own a PPC, you may remove the next line:
SetCacheMode 0x8027000 Size 0x3000 CacheInhibit  Valid

;If you don't own a PPC, you may remove the next line:
SetCacheMode 0x802A000 Size 0x7F56000 CopyBack  Valid

;SetCacheMode 0xFF80000 Size 0x80000 CacheInhibit Valid
;If you don't own a PPC, you may remove the next line:
SetCacheMode 0xFF80000 Size 0x80000 CacheInhibit  Valid

SetCacheMode 0x40000000 Size 0x11000000 CacheInhibit Valid IOSpace

;If you don't own a PPC, you may remove the next line:
SetCacheMode 0x40000000 Size 0x11000000 CacheInhibit IOSpace Valid

SetCacheMode 0x60000000 Size 0x10000000 CopyBack Valid IOSpace

;If you don't own a PPC, you may remove the next line:
SetCacheMode 0x60000000 Size 0x10000000 CopyBack IOSpace Valid

;The following memory region should be left blank
;according to the CBM design rules. It isn't...
SetCacheMode 0xFFF00000 Size 0x80000 CacheInhibit Valid IOSpace


;P5 fixes follow here:
;If you do not own a P5 board, you may remove the following lines
;
;Several P5 boards build a private MMU setup on boot
;using a kludge called the BOOT-MMU-Port. To run this
;kludge, the following external command is run from
;LIBS:mmu/ as all other external commands
;
;This command installs also other P5 relevant MMU settings
;Hence, for P5 boards, please keep it in place even if
;you *DO NOT* see the BOOT-MMU-Port.
;
P5Init

Overall I didn't notice much difference in behaviour and (in)stability of my system. It behaved as it was doing without the MMUlib. Working fine until I run PPC Warp3D games and the crashing starts.

trixster · 28 March 2020, 12:19

What are you trying to achieve?

So for example Mmulibs is used in the sonnet project to cache inhibit the ppc’s zorro memory range

spudje · 28 March 2020, 12:22

I basically hoped to get a more stable system

And with this thread I was hoping to get a bit more explanation of the MMU memory tables and what they mean / how they should look best. The documentation only explains the different types of memory but it sort of assumes you know what that means then or for what use cases they are suited.

macce2 · 03 April 2020, 01:26

I agree with spudje.
I, too, installed the MMUlib package on my A4000D 060 OS3.9 system, to get a more stable system overall, but don' t understand the Mmu tables configuration at all.
I think there are some problems with them that I can' t solve. However, I must admit I haven' t got much experience in programming in general.
I think the MMUlib package installer could be more "intelligent" .
If you have a bit more " exotic" hardware configuration, I guess there will be some problems.

Btw; if you have a Fastlane Scsi controller card installed ( like me), is there generally any reason / need to install the fixP5 patch / part ?
And if you have to use LoadResident and/ or LoadModule programs in startup, should the Move4k app be ran before them ?!

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mmulib and whdload	HanSolo	Coders. System	5	09 January 2015 14:25

28 March 2020, 12:19	#3
trixster Guru Meditating Join Date: Jun 2014 Location: England Posts: 2,337	What are you trying to achieve? So for example Mmulibs is used in the sonnet project to cache inhibit the ppc’s zorro memory range

28 March 2020, 12:22	#4
spudje Registered User Join Date: Dec 2014 Location: Netherlands Posts: 1,406	I basically hoped to get a more stable system And with this thread I was hoping to get a bit more explanation of the MMU memory tables and what they mean / how they should look best. The documentation only explains the different types of memory but it sort of assumes you know what that means then or for what use cases they are suited.

03 April 2020, 01:26	#5
macce2 Retro maniac Join Date: May 2005 Location: Finland Age: 49 Posts: 1,219	I agree with spudje. I, too, installed the MMUlib package on my A4000D 060 OS3.9 system, to get a more stable system overall, but don' t understand the Mmu tables configuration at all. I think there are some problems with them that I can' t solve. However, I must admit I haven' t got much experience in programming in general. I think the MMUlib package installer could be more "intelligent" . If you have a bit more " exotic" hardware configuration, I guess there will be some problems. Btw; if you have a Fastlane Scsi controller card installed ( like me), is there generally any reason / need to install the fixP5 patch / part ? And if you have to use LoadResident and/ or LoadModule programs in startup, should the Move4k app be ran before them ?!

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