13 May 2020, 11:28 | #1 |
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Chip RAM handling
Hi everyone, I'm currently trying to figure out how Chip RAM is handled in the classic Amigas (500/2000).
Here is the information I have gathered so far: I’ll refer to the different versions of Agnus as Ag512K, Ag1M and Ag2M depending on their DMA-Pointer width. There is the CPU Address Bus and the Agnus Address Bus. The CPU Address Bus can address directly Fast RAM and some Chips, like the CIAs. The CPU Address Bus is fed into Gary (A17-23) and Agnus. Ag512K and Ag1M have the inputs A1-A19 and Ag2M has an additional A20. The input A19 may be changed to A23 via the jumper JP2/J101, which is only useful for Ag512K and Ag1M. Ag512K and 1M act very similar, they both use the input A19 to select the memory bank via RAS0/1 and they both use a multiplexed address bus with 9 bit to choose the memory cell. The only difference between them is that the Ag512K has a DMA-Pointer with 18 bit and the Ag1M has a DMA-Pointer with 19 bit. Ag2M is a different beast and has a multiplexed address bus of 10 bit making the memory banks unnecessary, since it can address now the full 2 MB directly. So there is no bank selection via RAS anymore. It also has an DMA-Pointer with 20 bit. Gary usually activates the RAMEN signal when the address is between 000000 and 020000. But there is an input EXRAM which causes it to activate RAMEN also for C00000-D80000. This input can be connected to the Trapdoor Connector or set to GND via a second jumper JP7A/J500. So here is where I’m confused: I assume that the 19th bit of the Ag1M DMA-Pointer is used for memory bank selection via RAS0/1 as well. I haven’t found any hard evidence for this though.
I know a lot of questions, but I tried hard to find the answers myself without any luck, so I hope people with more practical experience can answer them. Thanks Alex |
13 May 2020, 14:35 | #2 |
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Some quick thoughts:
1. It's not as much about the Agnus as it is about the OS marking it as Chip RAM and then making a mess of things when software tries to use the "second 512k of Chip" that the 512k Agnus can't actually use as Chip RAM. Blitting around things in the wrong block of RAM and so on. 2. It is pseudo Fast because it is on the Chip RAM bus, thus any custom chip DMA will inhibit the CPU's access to the C00000 RAM. 4. You will either get bus noise or mirrored contents if you access non-existing RAM. 5. Check the 1.2 exec disassembly for a general idea on how it's detected. These detection routines were revised for 1.3 and later OSes, but as said, the general idea is there. http://wandel.ca/homepage/execdis/exec_disassembly.txt |
13 May 2020, 15:39 | #3 |
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Regarding 2. I think it is usable as actual chip ram, but the OS will not allocate it as such because it is detected (via cpu) to sit at C00000, thus addresses in this range will never be used as custom chip DMA pointers. You could of course do this deliberately, if you wanted to.
Last edited by hooverphonique; 13 May 2020 at 16:35. |
13 May 2020, 16:32 | #4 |
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Thanks for the quick answers.
Interestingly it seems to be "because of the OS" for most of my questions. But it makes of course perfect sense. Thanks for the link to the commented disassembly of exec. This is a goldmine. After taking a quick glance it seems that the detection is dealing heavily with mirrored memory as well, so maybe I can find the answer to my 3rd question in there. |
13 May 2020, 17:06 | #5 |
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Not answering any of the questions but on #1, I don't know why but this is also called "Ranger" RAM. AIUI there is a theory that this was the address space intended for VRAM and there because of the code named "Ranger" project which was Jay Miners version of the A2000 before Los Gatos was closed.
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13 May 2020, 18:26 | #6 | |
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Quote:
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14 May 2020, 07:32 | #7 |
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So based on the feedback I have create the following graphic:
And this are the 2 memory detection routines from exec in c-like pseudo code: Code:
int GetAmountOfChipRam() { memory[0]=0; const int signature = 0xF2D4B698; for(int i=0x1000; i<0x20000; i+=0x1000) { memory[i]=signature; if (memory[0]!=0) return i; } return i; } Code:
int GetAmountOfPseudoChipRam() { const int step = 0x40000; for(int i=0xC00000; i<0xDC0000; i+=step) { // Write to RAM or INTENA (0x1000-0xF66 = 0x9A) // If it is INTENA we disable all interrupts memory[i + step - 0xF66]=0x3FFF; // Read from RAM or INTENAR if (memory[i + step - 0xFE4] == 0) { // When 0 it may still be RAM or INTENAR // Try to set all interrupts, except master interrupt enable memory[i + step - 0xF66]=0xBFFF; // Read again INTENAR if (memory[i + step - 0xFE4] == 0x3FFF) { // Now we can be sure that we are manipulating Chip Registers // Disable all interrupts memory[i + step - 0xF66]=0x7FFF; return i - 0xC00000; } } } return i - 0xC00000; } Last edited by AlexBruger; 14 May 2020 at 07:57. |
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