raster dma cycles

[Wepl]

for a picture ripper I need to know how many dma words are read based on the values of ddfstop, ddfstrt and fmode during one line.
on ocs the following seems to work:

(ddfstop & $fe) - (ddfstrt & $fe) = words read

how looks the formula on aga for fmode=1 and fmode=3

or do I missing something else?

[Toni Wilen]

Above formula is only a special case, it won't work in real world with all programs.

First fetch cycle is simple: DDFSTRT & mask where mask = FC if OCS, FE if ECS/AGA.

Last cycle calculation is much more complex, DDFSTOP is point where internal flag "one more 'fetch block' to do" is set. It is not real stopping point. I am not sure if this is exactly right (UAE does not need this kind of calculation) but it should be something like this:

endpos = DDFSTOP & (chipset specific mask);
if (endpos > $D6)
 endpos = $D6 (Documentation says $D8, it can't be right)
lastfetch = (endpos + fetchunit - 1) & ~(fetchunit - 1)

fetchunit: OCS/ECS/FM0=always 8, AGA FM=1: lores=16, hires/shres=8, AGA FM 2: lores=32,hires=16,shres=8

FM 1 = FMODE register 1 or 2, FM 2 = FMODE register 3.

EDIT: Forgot one important part, above formula only gives first and last DMA slot but there can be complete idle bitplane fetch units in AGA modes.

OCS/ECS/FM0: as expected, AGA FM=1: lores=2x, AGA FM=2: lores=4x,hires=2x

2x means divide the result by 2 to get number of DMA fetches. 4x = divide by 4.

[Wepl]

Thanks a lot, but isn't it necessary to consider also the fixed dma slots appropriate the raster positions for ddfstrt.
Can it be that ddfstrt and ddfstop are setting only flags for the raster dma to start and stop? And the raster dma has fixed slots depending on lo/hi/shres settings. If flag is set it starts to transfer in each slot, if flag is cleared it stops after next transfer.
In this case I would also need to align ddfstrt for the calc (round up).

for ddfstrt
lores: +7 & fff8
hires: +3 & fffc
shres: +1 & fffe

for ddfstop (one access after stop)
lores: (+7 & fff8) + 8
hires: (+3 & fffc) + 4
shres: (+1 & fffe) + 2

then calc the diff
ddflen = ddfstop - ddfstrt

fetchunit in bits would be:
fmode=0 16
fmode=1/2 32
fmode=3 64

dma bits would be ddflen
lores: * 2 + fetchunit - 1) & ~(fetchunit - 1)
hires: * 4 + fetchunit - 1) & ~(fetchunit - 1)
shres: * 8 + fetchunit - 1) & ~(fetchunit - 1)

and then /8 to the get the bytes transfered?
idle cycles should be ok because fetchunit only rounds up the transfer sum

or is it maybe also necessary to adjust ddfstrt/stop if fmode>0 because in these case dma transfers are happen only during specific slots?

[Toni Wilen]

DDFSTRT does not have any resolution specific alignment requirements, it does not need to be aligned to "fetch unit". Only side-effect is BPLCON1 starting to work strangely (it has offset added) if DDFSTRT is not aligned.

There are games and demos that use "unaligned" DDFSTRT.

[Wepl]

I have done several tests and found the following to be working:

start = ddfstrt & $FE
stop = ddfstop & $FE

shres, fmode=0-3: ((stop – start + 6) & $F8) * 8 + 64

hires, fmode=0-2: ((stop – start + 6) & $F8) * 4 + 32
hires, fmode=3: ((stop – start + 14) & $F0) * 4 + 64

lores, fmode=0: ((stop – start + 6) & $F8) * 2 + 16
lores, fmode=1/2: ((stop – start + 14) & $F0) * 2 + 32
lores, fmode=3: ((stop – start + 30) & $E0) * 2 + 64

[Toni Wilen]

It may work but it still is only an approximation and a hack, it for example breaks when DDFSTOP is technically illegal value of $E0 or larger.

Why not simply match it with known hardware behavior?

[Wepl]

ok for ddfstop:

stop = ddfstop > $D6 ? $D6 : ddfstop & $FE

are there restrictions for ddfstrt too?

[Photon]

You can use (ddfstop-ddfstrt)/4 to get the word width for hires, ($10+ddfstop-ddfstrt)/8 for lores (from memory so check HRM). I'm pretty sure this will handle all screens opened with the OS and legal HW-opened displays.

Since the registers wrap around you can get legal values resulting in no display at all, and illegal values accidentally resulting in a "correct" display. If you want to rip from really old demos you may want to support at least the latter case, since some coders didn't have proper docs and some just changed the values until the display looked correct.

[PiCiJi]

First fetch cycle is simple: DDFSTRT & mask where mask = FC if OCS, FE if ECS/AGA.

I have found some info in following document:
http://palbo.dk/dataskolen/maskinspr.../letter_04.pdf

it reads:
Remember that if DDFSTRT does not end with $0 or $8 then it is rounded down
for hires $4 or $c for last nibble.

Is this info right for OCS?
If I understand you right Toni, a lores fetch can even start at 4 or 0xC for the last nibble and hires at 0 or 8 ?

[Photon]

Yes, Toni (and HRM) is correct and the pdf is wrong. Actually, since they show the bits of the DDF registers, I think they just wanted to help readers align a hires display better.