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Old 05 May 2022, 07:14   #181
Mathesar
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Originally Posted by TymoDEV View Post
Great job. Looks very nice on the new accelerator card. I am considering to buy it. I already knew the simple turbo x2 system before.
Is it possible to work with 68HC000FN20 at turbo x4 [28 MHZ]?
I am dreamming about turbo x4 version. If it would be possible?
There is this one: http://irixlabs.com/hc508
and this one: https://amigastore.eu/597-wicher-508i-accelerator.html
and this one for A500 available as open source https://github.com/PR77/A500_ACCEL_RAM_IDE-Rev-2

Plenty of options available and all much better than my design. The only real attraction of my design is that it uses no programmable logic or any other exotic components making it a nice DIY project. It also uses sort of "period correct" components making it look like this could have been designed in the late 80's.
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Old 06 May 2022, 18:50   #182
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Can you make a correction to x4 in your design by changing the turbo PLL 4046 system to another one?

Quote:
The only real attraction of my design is that it uses no programmable logic or any other exotic components making it a nice DIY project. It also uses sort of "period correct" components making it look like this could have been designed in the late 80's
That's why I prefer this design to modern-looking

Last edited by TymoDEV; 11 May 2022 at 12:44.
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Old 26 May 2022, 10:00   #183
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The SE edition

I have designed a new version of the 14MHz accelerator, the "SE" edition.
SE stands for "sidecar edition", "special edition", "snail edition" or whatever you like to call it.

The big new feature is that it should now support DMA so that SCSI sidecars like the A590 are supported. It also gets rid of the fast RAM to reduce cost and because it proved to be a bit useless anyway if one has additional fast RAM installed like in an A590. And finally the new design uses a DIP64 68000 CPU so one can try to overclock the original CPU to reduce costs even further. The whole design uses only 5 standard "old school" logic chips and should accelerate an A500 by about 60% if there is fast RAM installed. I will release it as open source once I have built and tested it.

Anyway, since I just finished routing this board I wanted to share this little preview:
Click image for larger version

Name:	14MHz_SE_preview.png
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Old 26 May 2022, 15:48   #184
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I have designed a new version of the 14MHz accelerator, the "SE" edition.
Great stuff, this will be perfect for my a590. It will probably work with the a2091 too.
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Old 26 May 2022, 16:57   #185
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Cool Thanks.
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Old 08 August 2022, 06:44   #186
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Originally Posted by Mathesar View Post
I have designed a new version of the 14MHz accelerator, the "SE" edition.
SE stands for "sidecar edition", "special edition", "snail edition" or whatever you like to call it.

The big new feature is that it should now support DMA so that SCSI sidecars like the A590 are supported. It also gets rid of the fast RAM to reduce cost and because it proved to be a bit useless anyway if one has additional fast RAM installed like in an A590.

Aww! I was just about to ask how you fixed DMA. :-)

I'd like to try and bring up the 14MHz accelerator but with local RAM and fixed DMA hacks, which if I read the schematic right, is running at 14MHz and not locked at 7MHz.

Last edited by erikarn; 08 August 2022 at 19:51. Reason: I woke up and re-checked things. :-)
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Old 09 August 2022, 20:02   #187
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Aww! I was just about to ask how you fixed DMA. :-)

I'd like to try and bring up the 14MHz accelerator but with local RAM and fixed DMA hacks, which if I read the schematic right, is running at 14MHz and not locked at 7MHz.
Yes, I fixed the DMA (I think... as it is untested). What i basically did is add tristate support to the _AS signal using a 4066. However, there is no local RAM support anymore. I am currently on vacation but I can give you all the schematics when I get home. You are right that the local ram runs at 14Mhz instead of 7Mhz. However, it could still be made DMA-able. Firstly you need to feed the 7MHz _AS into the RAM controller. If you read back in this thread you'll see what I mean. Secondly the RAM needs to be moved to another address somewhere in ZII space to avoid interference with gary decoding the C00000 address. This could be done using just some rewiring of the address decoder, no extra components needed. The RAM then needs to be added via addmem during bootup. However, this means that some early stuff will end up in the slower fast mem on the A590. You'd still see a speed improvement though.

But, this is all untested. I am currently spendig my hobby time on a bitbanging SPI interface for the A500 to support SD cards and a network device. The prototype is working (see here http://eab.abime.net/showpost.php?p=...3&postcount=13 ). You can try however
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Old 10 August 2022, 02:06   #188
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Yes, I fixed the DMA (I think... as it is untested). What i basically did is add tristate support to the _AS signal using a 4066. However, there is no local RAM support anymore. I am currently on vacation but I can give you all the schematics when I get home. You are right that the local ram runs at 14Mhz instead of 7Mhz. However, it could still be made DMA-able. Firstly you need to feed the 7MHz _AS into the RAM controller. If you read back in this thread you'll see what I mean. Secondly the RAM needs to be moved to another address somewhere in ZII space to avoid interference with gary decoding the C00000 address. This could be done using just some rewiring of the address decoder, no extra components needed. The RAM then needs to be added via addmem during bootup. However, this means that some early stuff will end up in the slower fast mem on the A590. You'd still see a speed improvement though.
Yeah, that's kinda what I thought. I've bought the bits to populate the accelerator i have here with RAM and I'll get that going, and then I'll try to hack in the DMA support and test it.

Thanks! Lmk when you're back and have schematics to share!
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Old 10 August 2022, 12:19   #189
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@Mathesar

i am planning on using this accelerator in an A1000. Currently I have installed a Ram/IDE68k, which gives me an IDE interface + 8MB of FastRAM (beginning at 00200000)
Can you tell me if its possible to put your accelerator on top of my existing expansion?

Thanks!
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Old 10 August 2022, 18:06   #190
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What is nice with the old design is that you can use the expansion memory as chip memory with a quite easy mod.
I understand that the new design will be very cheap but also a bit slower.
With the old design it is also possible to disable fast RAM and run stock speed.
Anyway, good to have alternatives as this design will give other possibilities regarding HDD etc.
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Old 10 August 2022, 20:19   #191
Mathesar
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@Mathesar

i am planning on using this accelerator in an A1000. Currently I have installed a Ram/IDE68k, which gives me an IDE interface + 8MB of FastRAM (beginning at 00200000)
Can you tell me if its possible to put your accelerator on top of my existing expansion?

Thanks!
As long as you have no DMA enabled devices in your system (SCSI cards) I see no reason it would not work.

However it has never been tested with that card and I have heard some reports it doesn't work with some similar IDE controllers. Why I don't know, probably some timing issue. On my system it works with the new SPI controller I'm working on and Mika's diy IDE controller.
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Old 10 August 2022, 22:15   #192
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Thanks for the answer. Is there an estimated release date?
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Old 11 August 2022, 20:31   #193
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Thanks for the answer. Is there an estimated release date?
You could use the current version with or without the 1MB "ranger" RAM populated. That is a tested design. The new design would add nothing in your setup apart as you do not seem to have any DMA devices on the bus. As I have too many projects on my plate I won't have time in the near future to test the SE version but I will try to make some time after my vacation to upload it to github.
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Old 17 August 2022, 20:27   #194
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Thanks for the answer. Is there an estimated release date?
https://github.com/Mathesar/14mhz-accelerator-SE

Note: All untested at this point!
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Old 22 August 2022, 07:03   #195
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ok, so now that I have a mostly working amiga 2000 here with a GVP SCSI card, guess I can test out DMA. :-)

So, once I get the CPU extender riser I'll do this:

> You're right. the problem is that ~AS7 is not tristated as it is driven from the HCT74.
> If you are feeling experimental, this is what you could do:
> implement a pseudo-tristate by making ~AS7 an open-collecter output. Lift pin 6 of U5 and then solder a schottky diode (BAT85 or something similar) from pin 6 to ~AS on the host
> connector. The diode arrow must point to pin 6 (kathode on pin6, anode to ~as to host connector). It is not pretty but this way the GVP should be able to drive ~AS as well.
> With above mode, DMA should work with the fast $C00000 RAM disabled. To also make the $C00000 ram work do the next mod as well:
> lift pin 10 of U8 and solder a jumper wire from pin 10 to ~as on the host connector. This will make the onboard reachable from the GVP.

* Try your 4066/02 logic to tri-state /AS_7, I'll go build that on a little breadboard. Should U5A pin 6 (/Q) still feed U4A pin 3, on its way to control /DTACK_14 ? It looks like I should leave that all hooked up. (I'll likely just go cut the /AS_7 track to the plug header and run a wire...)
* lift pin 10 of U8 (That's going to VCC) and wire it to /AS_7 ? That'll either be driven by the 14MHz 68000, or if a bus dma grant is requested, when the bus master asserts /AS ?

Thanks!


-a
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Old 27 August 2022, 20:23   #196
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* Try your 4066/02 logic to tri-state /AS_7, I'll go build that on a little breadboard. Should U5A pin 6 (/Q) still feed U4A pin 3, on its way to control /DTACK_14 ? It looks like I should leave that all hooked up. (I'll likely just go cut the /AS_7 track to the plug header and run a wire...)
Yes, U5A pin 6 should still go to U5B pin 13. So it is indeed best to cut /AS7 at the plug header.

Quote:
* lift pin 10 of U8 (That's going to VCC) and wire it to /AS_7 ? That'll either be driven by the 14MHz 68000, or if a bus dma grant is requested, when the bus master asserts /AS ?
Yes indeed! That's the plan!
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Old 04 September 2022, 04:45   #197
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Yes, U5A pin 6 should still go to U5B pin 13. So it is indeed best to cut /AS7 at the plug header.

Yes indeed! That's the plan!
ok, so:

* amiga 500 - everything is a-ok
* amiga 2000 w/ 2.04 roms - yellow w/ the RAM jumpers on the board, and magenta without them.

it's installed in the CPU accelerator slot with the boss jumper set on this adapter board.

Any suggestions on what info I should go gather? I do have a logic analyser here somewhere..
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Old 09 September 2022, 20:16   #198
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Mathesar: Here is your accelerator

[ Show youtube player ]
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Old 10 September 2022, 08:41   #199
Mathesar
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Mathesar: Here is your accelerator

[ Show youtube player ]
I brought my A500 to a local retro computerclub some time ago with the accelerator installed. It was running the free demo of Dread. While I was chatting with someone two guys started playing Dread and commented to each other how smooth it runs a bog standard A500. I didn't ruin it for them...
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Old 10 September 2022, 08:50   #200
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ok, so:

* amiga 500 - everything is a-ok
* amiga 2000 w/ 2.04 roms - yellow w/ the RAM jumpers on the board, and magenta without them.

it's installed in the CPU accelerator slot with the boss jumper set on this adapter board.

Any suggestions on what info I should go gather? I do have a logic analyser here somewhere..
I never tested in an A2000 and I don't know the adapter board. What I can remember though when making it work on the A500 is that the CIA timing was the most critical. So maybe that is something to check first. Also, I would suggest booting from Chucky's Diagrom. The fact that you get a yellow or magenta screen means that at least the CPU is doing something!
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