A4000 IDE registers

mark_k · 23 March 2015, 21:16

How are the A4000 IDE controller registers mapped? NetBSD gayle.h mentions
#define GAYLE_IDE_BASE_A4000 0xDD2020
#define GAYLE_IDE_INTREQ_A4000 0x1000 /* with stride of 1 */
and the code I'm disassembling seems to read or write at $DD2020 plus
0, 8, 12, $1C, $1006, $100A, $100E.

So I guess the IDE registers are mapped as bytes every 4 bytes in Amiga address space. But what are the $1000+ offset registers for?

hooverphonique · 24 March 2015, 10:59

that's strange, because A4000 doesn't use Gayle for IDE, but maybe Gayle and A4000 IDE are compatible register-wise.

Anyway, the A4000T functional spec mentions a little about A4000 IDE and the registers.
http://amiga.serveftp.net/Schematics...cification.pdf

Toni Wilen · 24 March 2015, 11:43

Register spacing is 4 bytes (both Gayle and A4000)

+$1000 should map to IDE CS1 line (access to Alternate Status/Device Control register which is register 6 and Drive Address [DA is ATA1-only] which is register 7)

Are you sure you about all $1xxx offsets? They look strange.. Byte or Word accesses?

Gayle or not Gayle does not make much difference, basic IDE is nothing more than address decoder that maps some physical m68k addresses to IDE register addresses + interrupt handling (which is the only chip specific operation).

hooverphonique · 24 March 2015, 13:15

Quote:

Originally Posted by Toni Wilen

Gayle or not Gayle does not make much difference, basic IDE is nothing more than address decoder that maps some physical m68k addresses to IDE register addresses + interrupt handling (which is the only chip specific operation).

you are right, I should have said address-wise instead of register-wise

mark_k · 24 March 2015, 13:36

Byte accesses. I'm trying to understand the DataFlyer 4000 SCSI+ driver code. The DataFlyer 1200 SCSI+ code differs by only a few bytes due to the different IDE base address. [The wrong driver disk is linked on the amiga.resource.cx page. The correct driver is http://www.l8r.net/install/hard_driv...erScsiPlus.DMS.]

Those products are a bit weird/interesting. A small board which contains a 5380 SCSI chip and one other chip (a PAL/GAL I assume), and connects to the A4000 IDE port. So the driver code accesses the 5380 via the IDE port registers somehow. (The driver code is a bit difficult to follow. Written by the same developer who did the old C Ltd SCSI software. Too many files/layers, though this time they're all in a single driver file.)

Anyway, here are a couple of code fragments that access $1000+ registers.

Code:

IssueIdentifyDrive	MOVE.B	#8,($101A,A4)
	BSR.W	CheckForDrive
	BNE.B	.ReturnMinus1

	MOVE.W	#$EC,D0	;$EC = IDENTIFY DRIVE
	BSR.W	WriteDriveHeadRegAndIssueATACommand
	BNE.B	.ReturnMinus1

	BSR.W	lbC001D08
	BNE.B	.ReturnMinus1

	BSR.W	WaitUntilNotBusyWithTimeout
	BNE.B	.ReturnMinus1

	MOVE.B	($1C,A4),D0	;Read Status Register
	ANDI.B	#%11101001,D0	;Look at busy, drive ready, drive write fault, data request, error bits
	EORI.B	#%01001000,D0	;Want drive ready and drive seek complete bits to be set, others clear
	BNE.B	.ReturnMinus1

	MOVEQ	#0,D0
	RTS

.ReturnMinus1	MOVEQ	#-1,D0
	RTS



CheckForDrive	MOVEM.L	D0/D1/A2,-(SP)
	LEA	($9E,A5),A2
	MOVE.B	($33,A3),D0
	BEQ.B	lbC001E8E

	LEA	($AE,A5),A2
lbC001E8E	ORI.B	#%10100000,D0	;Set the must-be-1 bits
	MOVE.B	D0,($18,A4)	;Write to Drive/Head Register
	MOVE.B	#8,($101A,A4)
	BSR.W	WriteToDriveHeadRegWaitUntilNotBusy
	BNE.B	.ReturnMinus1

lbC001EA2	MOVE.B	D0,(12,A4)	;Write to Sector Number Register
	TST.L	(_custom+intenar).L
	CMP.B	(12,A4),D0	;Read Sector Number Register
	BNE.B	.ReturnMinus1

	ADDQ.B	#1,D0
	ANDI.B	#31,D0
	BNE.B	lbC001EA2

.Return	MOVE.B	D0,(14,A2)
	MOVEM.L	(SP)+,D0/D1/A2
	RTS

.ReturnMinus1	MOVEQ	#-1,D0
	BRA.B	.Return



WriteDriveHeadRegAndIssueATACommand
	MOVE.B	($33,A3),D1
	ORI.B	#%10100000,D1	;Set the must-be-1 bits
	MOVE.B	D1,($18,A4)	;Write to Drive/Head Register

IssueATACommand	MOVE.B	#8,($101A,A4)
	MOVE.B	($1C,A4),D1	;Read Status Register
	ANDI.B	#%11000000,D1	;Look at BSY and DRDY bits
	EORI.B	#%01000000,D1	;Want BSY = 0, DRDY = 1
	BNE.B	.ReturnMinus1

	MOVE.B	D0,($1C,A4)	;Write to Command Register
	MOVEQ	#0,D0
	RTS

.ReturnMinus1	MOVEQ	#-1,D0
	RTS



lbC001D08	MOVE.W	#300,D1
	BSR.W	ReadCiaaTODPlusD1
lbC001D10	BSR.W	HasTimeoutExpired
	BCC.B	.TimeoutNotExpired

	BSR.B	lbC001D50
	MOVEQ	#-1,D0
	RTS

.TimeoutNotExpired	MOVE.B	#5,($100E,A4)
	MOVE.B	#0,($1006,A4)
	MOVE.B	#15,D0
	AND.B	($100E,A4),D0
	CMPI.B	#5,D0
	BNE.B	lbC001D10

	MOVE.B	#10,($100E,A4)
	MOVE.B	#0,($1006,A4)
	MOVE.B	#15,D0
	AND.B	($100E,A4),D0
	CMPI.B	#10,D0
	BNE.B	lbC001D10


lbC001D50	MOVEQ	#0,D0
	MOVE.B	D0,($1006,A4)
	MOVE.B	D0,($100A,A4)
	MOVE.B	D0,($100E,A4)
	RTS

Toni Wilen · 24 March 2015, 13:43

Quote:

Originally Posted by mark_k

Those products are a bit weird/interesting. A small board which contains a 5380 SCSI chip and one other chip (a PAL/GAL I assume), and connects to the A4000 IDE port. So the driver code accesses the 5380 via the IDE port registers somehow. (The driver code is a bit difficult to follow. Written by the same developer who did the old C Ltd SCSI software. Too many files/layers, though this time they're all in a single driver file.)

Sounds interesting

I guess it uses CS1=1 unused register space (0 to 5, probably up to 7, those two IDE registers are not really needed) to access 5380 registers. Like IDE doublers use CS1=1 to access secondary IDE.

Toni Wilen · 11 May 2015, 17:05

DataFlyer SCSI+ is now emulated, here is quick description how it works (My guess above was wrong):

Unused ATA Control block registers 0 to 5 are used to control DataFlyer hardware state.

Register 0: byte wide SCSI "fake dma" data port.
1 to 3: Used to check if ATA IRQ line is active. (See ".TimeoutNotExpired" in above disassembly). No idea how it really works and why the check is so complex.. Possibly have other uses?
4: Read access selects SCSI mode.
5: Read access selects ATA mode.
6 and 7: Normal ATA Alternate Status/Device Control and Drive Address registers.

DataFlyer ATA mode = ATA register space work normally.
DataFlyer SCSI mode = ATA register space replaced with 53C80 registers (ATA register 0 = 53C80 register 0 and so on)

Enabling either mode will also disconnect ATA IRQ line from Gayle/A4000 mainboard. DataFlyer does not use interrupts. (Any ATA IRQ would just hang the system because DataFlyer driver also kills original scsi.device interrupt handler)

Reverse-engineering by me and mark.k.

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23 March 2015, 21:16	#1
mark_k Registered User Join Date: Aug 2004 Location: Posts: 3,351	A4000 IDE registers How are the A4000 IDE controller registers mapped? NetBSD gayle.h mentions #define GAYLE_IDE_BASE_A4000 0xDD2020 #define GAYLE_IDE_INTREQ_A4000 0x1000 /* with stride of 1 */ and the code I'm disassembling seems to read or write at $DD2020 plus 0, 8, 12, $1C, $1006, $100A, $100E. So I guess the IDE registers are mapped as bytes every 4 bytes in Amiga address space. But what are the $1000+ offset registers for?

24 March 2015, 10:59	#2
hooverphonique ex. demoscener "Bigmama" Join Date: Jun 2012 Location: Fyn / Denmark Posts: 1,643	that's strange, because A4000 doesn't use Gayle for IDE, but maybe Gayle and A4000 IDE are compatible register-wise. Anyway, the A4000T functional spec mentions a little about A4000 IDE and the registers. http://amiga.serveftp.net/Schematics...cification.pdf

24 March 2015, 11:43	#3
Toni Wilen WinUAE developer Join Date: Aug 2001 Location: Hämeenlinna/Finland Age: 49 Posts: 26,574	Register spacing is 4 bytes (both Gayle and A4000) +$1000 should map to IDE CS1 line (access to Alternate Status/Device Control register which is register 6 and Drive Address [DA is ATA1-only] which is register 7) Are you sure you about all $1xxx offsets? They look strange.. Byte or Word accesses? Gayle or not Gayle does not make much difference, basic IDE is nothing more than address decoder that maps some physical m68k addresses to IDE register addresses + interrupt handling (which is the only chip specific operation).

11 May 2015, 17:05	#7
Toni Wilen WinUAE developer Join Date: Aug 2001 Location: Hämeenlinna/Finland Age: 49 Posts: 26,574	DataFlyer SCSI+ is now emulated, here is quick description how it works (My guess above was wrong): Unused ATA Control block registers 0 to 5 are used to control DataFlyer hardware state. Register 0: byte wide SCSI "fake dma" data port. 1 to 3: Used to check if ATA IRQ line is active. (See ".TimeoutNotExpired" in above disassembly). No idea how it really works and why the check is so complex.. Possibly have other uses? 4: Read access selects SCSI mode. 5: Read access selects ATA mode. 6 and 7: Normal ATA Alternate Status/Device Control and Drive Address registers. DataFlyer ATA mode = ATA register space work normally. DataFlyer SCSI mode = ATA register space replaced with 53C80 registers (ATA register 0 = 53C80 register 0 and so on) Enabling either mode will also disconnect ATA IRQ line from Gayle/A4000 mainboard. DataFlyer does not use interrupts. (Any ATA IRQ would just hang the system because DataFlyer driver also kills original scsi.device interrupt handler) Reverse-engineering by me and mark.k.

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