03 August 2016, 04:47 | #1 |
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Enhanced 68k ISA
I was recently asked some questions about the enhanced 68k ISA I worked on a few years ago but my old documentation is no longer available elsewhere. I have added the 68kF_PRMv7.pdf as an attachment. Sorry that pdf is the only recognized EAB attachment that works well.
First a little history. I was contacted by Gunnar and asked to join the Apollo Team and help create an enhance FPGA 68k CPU which I did. I took the initiative, without being asked, to document ISA enhancements to help evaluate 68k ISA ideas for the apollo-core.com FPGA project. Originally I named the document ApolloPRM but decided it would be advantageous to have an ISA usable by other 68k FPGA processors also. I came up with the 68kF (68koolFusion) name with the idea to sound like kool fun and the Fusion part being a fusion of 68k and ColdFire. It turns out the ISA is more like cold Fusion as it fissiled when Gunnar decided he was going to make all the decisions himself while abandoning all previous work and our work group ideas. I cleaned up the documentation a little recently including some new ideas and going back to the extended precision FPU (which I favor especially for compatibility). I added the ColdFire BYTEREV and BITREV as REVB.L (Reverse Bytes) and BREV.L (Bit Reverse) respectively which was talked about in another thread including mentioning the possibility of fusing with a MOVE.L. I tried to create a REVB.W using ROR.W #8,Dn but the CC would be set differently so it wouldn't have been consistent. One of the last changes was for BScc (Bit Set Condition) including the name change as suggested my meynaf to better match the 68k naming conventions. I came up with an idea to add an operation to the other bits but I don't know the best syntax to specify it. Two bits in the encoding can easily be used to specify an operation on the other bits including no operation, change the bits, clear the bits and set the bits. I believe this would be a simple enough operation but makes the instructions much more powerful. The following are some ideas of possible syntax to set or clr bit #0 according to CC while clearing other bits. Code:
bsne #0:clr_other,(a0) bsne #0,(a0),clr_other bsne_clr #0,(a0) Last edited by matthey; 11 August 2016 at 23:42. |
03 August 2016, 07:54 | #2 |
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This one can be fun. Off the top of my head, two things I'd be happy to see:
1. cmove is one instruction I came to enjoy while away from the Amiga. Conditional moves instead of the usual 68k bcc, move combination are quite convenient, at least in Asm code. Edit: found SELcc 2. One of the favorite toys of you Apollo guys is missing from the PDF: the SIMD stuff. Otherwise, thank you for the update regarding the ISA. Which brings me to one more thing: How can one reliably detect a CPU with the feature set in question (at different core development levels)? Do we have to probe instruction by instruction or is there already something like "CPUID"? Last edited by buggs; 03 August 2016 at 08:03. |
03 August 2016, 10:48 | #3 | |||||||
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Adding a conditional move instruction wouldn't help for code density because it would have to be a 32-bit instruction (due to lack of encoding space for it). Nice in theory, but the most common case i've found was the choice between two immediates or two memory addresses (LEA)... Quote:
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1. Your ABS instruction documents a 4-bit field for the register, while saying it works on Dn. To the best of my knowledge you didn't add extra data registers so it ought to be a 3-bit field. 2. You document longword only for ADDQ to address regs. But word size exists and is used in programs - even though it's useless as it leads to exactly the same result. 3. You have a branch hint bit. Do you remember what Gunnar said about what occured with this bit in the Power cpu ? You are a compiler writer so you should know that the compiler doesn't have this kind of info, btw. 4. You used Gunnar's dirty encoding for DBcc.L. This ain't good for assemblers and disassemblers and isn't overall nice. Just set b7=b6=0 from normal DBcc and you're done. 5. Perhaps you could simply mention REMU/REMS as alias for DIVUR/DIVSR, instead of having one entry for each. 6. How could you enable (An)+ and -(An) for JMP/JSR ? It's unsized, so what's the operation ? Same for LEA/PEA. 7. SATS is useless. Yes, really. I can develop if you want. Clearly I wouldn't have put it. 8. You seem to be moving 4-bit condition fields here and there. That's no good. At least BScc and SELcc should have it at the same place. 9. I don't see SELcc as very useful. One could just preload the target register with case 1, then test the condition, then conditionnally load the target with case 2. Not fully against it, but the encoding really isn't nice. Quote:
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I start by adding the Coldfire's useful stuff : MVZ, MVS, BITREV, BYTEREV. Write to PC-relative is now allowed, unless (like in the case of Scc) the encoding has been stolen. Address regs are supported whereever this has a natural encoding and that encoding isn't stolen by something else (i.e. not for Scc). This means you can now do MOVEA.B to use the same extend trick as MOVEA.W. Note : unsigned extend (more common for bytes). Code:
0001<r>0 01< ea > movea.b ea,An Code:
00101001 11< ea > movem.b ea,rlist 00111001 11< ea > movem.b rlist,ea Therefore the byte index is added. If compatibility didn't have to be maintained, i'd have done this otherwise. Code:
110<r> d<r>0ss1 00111000 (an,dn.b) 110<r> d<r>0ss1 00111010 d16(an,dn.b) 110<r> d<r>0ss1 00111011 d32(an,dn.b) 111011 d<r>0ss1 00111010 d16(pc,dn.b) 111011 d<r>0ss1 00111011 d32(pc,dn.b) Code:
111101 d32(pc) Alas it needs OS patches to be saved and therefore i won't defend this much. Like SP, it could have a different value for user and supervisor, hence the UBP here. Thus : Code:
111110 d16(bp) 111111 d8(bp,ix) 01001110 01111010 d<r>1111 11111111 movec bp,rn (base pointer) 01001110 01111011 d<r>1111 11111111 movec rn,bp 01001110 01111010 d<r>1111 11111110 movec ubp,rn (user base pointer) 01001110 01111011 d<r>1111 11111110 movec rn,ubp The new mode makes the bit-field behave like this : - for the position, we name the bit like for BTST (and it's the last bit of the field we target here) ; the operation is limited to 32 bits - for the size, we use (32-n) This gives the following bit-field word extension encoding : Code:
b15 D/A b14-12 reg b11 static/dynamic b10 mode reverse (pos) b9 D/A (pos) b8-6 reg (pos) b5 static/dynamic b4 mode reverse (len) b3 D/A (len) b2-0 reg (len) Anyone knowing the x86 well enough knows the LEA to EAX trick. There you can do it as well. Also remember you can do things such as MOVE.x (Dn.l),ea - for the cases you're short of address regs. Code:
0100<r>1 01< ea > lea ea,Dn ABS is like in Matt's doc. BITCNT is called POPCNT but i don't like this name. Even if it's more or less "standard issue", we count bits, not people. DUP will duplicate the lowest byte into all others, i.e. $12345678 will become $78787878. Code:
00000000 11001<r> dup Dn 00000010 11001<r> abs Dn 00000100 11001<r> bitcnt Dn Hence the TAC (Test And Clear) instruction, testing the byte like TST.B and clearing it. Code:
00011001 11< ea > tac ea Dynamic bit-test a constant is a nice trick, however limited to 8 bits. This limits will go away. Code:
01001011 11000<r> btst Dn,#i16 01001101 11000<r> btst Dn,#i32 MOVE.L #16bit,Dn can be handled with LEA adr.w,Dn. ADD/SUB are useful but relatively rare. OR/AND/EOR are useless - just operate on the lower part of the reg. CMP is quite useful but we can add it alone : Code:
01001000 01100<r> cmpq.l #i16,Dn In addition it works on the lower word only and having it sometimes on the high word would spare a register. I'm not sure full DBcc.L is really useful even though i have an encoding for it. I've put simple DBF.L here, this probably needs discussion. Code:
01000001 11000<r> dbfh Dn,d16 (high word dbf) 01000011 11000<r> dbf.b Dn,d16 01000101 11000<r> dbf1 Dn,d16 (base 1 dbf) 01000111 11000<r> dbfa An,d16 (dbf An) 01001111 11000<r> dbf.l Dn,d16 I prefer having an integer SQR, and here it is. May be complicated to do in HW but if it can be done in FP, it can be done in integer. Code:
1100<r>1 10000<r> sqr Dn,Dn (sqr(64) -> 32) I don't see targeting other bits as useful and my encoding is different, but Matt's doc explains it quite well. Code:
00001110 11< ea > <cc>0100 00i< n > bs<cc> #n/Dn,ea (bit set from cc) It means you can do ROR.B a0,8(a1) if you want. Code:
00001110 tt< ea > 00oos100 00i< n > shift.t #n/Rn,ea Still, a 32-bit version can be useful. Code:
00001110 tt< ea > 0<r>0101 00000000 eor.t ea,Dn And so, even though it's quite a large instruction (again due to encoding space constraits), i add it : Code:
00001110 tt< ea > 0<r>0101 01000000 exg.t ea,Dn RTS is done only if condition is true, else NOP. Code:
1110<cc> 11111100 rts<cc> If compares the byte in the source register, to all 4 bytes in the target register. If found, it puts the index of that byte (0 to 3) in the target register and sets the CCR accordingly. Code:
0100<r>1 11001<r> mbcmp Dn,Dn Code:
00001110 11< ea > a<r>0100 0100a<r> mix ea,rn:rn Code:
00001110 11< ea > 0<r>s100 10i< n > rxl/rxr #n/dn,dn:ea Ouch. What a large post. I have a few other instruction ideas but that's all for now. I don't expect positive feedback ; cpu discussions often end up in flame wars. But who knows. |
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03 August 2016, 17:32 | #4 | |
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http://www.apollo-core.com/index.htm?page=instructions The SELcc instruction from the 68kF ISA is simpler than a CMOVcc style instruction but the instruction can be large and may be unnecessary with predication like the Apollo core has. It needs further evaluation especially in regards to how well compilers could use it. CMOVcc is often no better for more modern x86/x86_64 processors. A query system for hardware capabilities was discussed but it was not a priority. The ColdFire added it although their system would be inadequate for enhanced 68k processors. ARM has a nice query system but needs it with an overload of variations. I would hope an enhanced 68k would have a more standard set of hardware (SoC) and not as many variations considering it doesn't need to support low end embedded processors where it is not competitive. |
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03 August 2016, 18:30 | #5 |
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I think it would be very useful to have a conditional BSR, "BSRcc". Essentially a Bcc where you can do rts to get back. Would allow for much cleaner code. Or can you use a macro with some local labels to do this somehow?
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03 August 2016, 19:18 | #6 | |
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bsreq macro ; bsr if eq bne .\@ bsr \1 .\@ endm |
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03 August 2016, 21:04 | #7 | ||||||||
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Sometimes what i want to do is conditional AND or OR with register. Like Scc but only sets to -1 (OR) or clears (AND). Last edited by Mrs Beanbag; 03 August 2016 at 21:24. |
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03 August 2016, 21:36 | #8 | |||
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I planned an immediate mode (but forgot it here). Perhaps even better than the register mode : Code:
01001110 10000<r> mbcmp dn,#i32 (disables write ; only sets ccr) 01001110 11000<r> mbcmp #i8,dn Code:
cmpi.b #$a9,d0 beq found cmpi.b #$98,d0 beq found cmpi.b #$11,d0 beq found cmpi.b #$fe,d0 beq found Code:
mbcmp d0,#$a99811fe beq found The 68k isn't especially good in range-limiting values (aka saturation). So my conversion functions take care about that. If unsigned, values <0 become 0 and values >$ff (for byte) or $ffff (for word) become $ff(ff). If signed, values <0 become $ffffff80 or $ffff8000, and values >$7f or $7fff become $7f(ff). This allows doing the computation with the full register size and then convert back to the normal size at the end of the process. Code:
01001110 1w000<r> cnvu.bw dn 01001110 1w001<r> cnvs.bw dn I don't get it. Can you be more precise ? |
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03 August 2016, 21:45 | #9 |
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ok. i mean...
* set a byte to -1 if the condition is met, otherwise leave unchanged, or * clear a byte to 0 if the condition is not met, otherwise leave unchanged I was looking at the 88000 instruction set the other day and it had "pixel" instructions, presumably (i didn't read in detail) for working with 32-bit RGBA values. |
03 August 2016, 22:10 | #10 | ||
son of 68k
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scc dn ; dn is tmp or.b dn,dest Code:
scc -(sp) or.b (sp)+,d0 Quote:
Say, something like 16-bit argb to 32-bit argb or vice versa. It's straightforward but a little bit cumbersome. Yet it doesn't value creating a new instruction especially for it. However, the x86 has the quite interesting parallel bit extract/deposit (PEXT, PDEP) which would be wonders for this and other tasks. Think of them as PACK/UNPK with variable bit pos. I don't like x86 too much but these two look like gems to me. |
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04 August 2016, 00:35 | #11 | |||||||||||||||||||||||||||||||
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it is at least worth considering. There may be some complexity in the implementation though. Quote:
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It doesn't makes much sense if a 64 bit register could be rotated. You are not kidding about the long post. It has taken forever to respond. We should probably narrow down the number of topics to discuss. Last edited by matthey; 04 August 2016 at 00:58. |
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04 August 2016, 08:15 | #12 | ||
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04 August 2016, 10:26 | #13 | |
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Anyway BITREV doesn't just operate on a byte, it operates on an entire register. Reversing a single bit wouldn't do very much! BFREV would make sense for a bitfield reverse, however... |
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04 August 2016, 11:18 | #14 | ||||||||||||||||||||||||||||||
son of 68k
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But is a free addq/subq #4 worth all that encoding space ? Quote:
The problems of SATS are : 1) It works only for signed stuff. Its algorithm can't work at all for unsigned. 2) It works after a single op which must be ADD/SUB. Yet the data comes out of many operations which can individually overflow for better precision, so clamping should be done at the very end of the process. Quote:
Yet for BScc it's impossible to use the normal place unless reclaiming line-A, and if you add SELcc on top of this, better have as few different pos as possible. Quote:
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Or even SWAP.B (where the current SWAP is SWAP.W). Quote:
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On the contrary, bytes are very, very commonly used as index. And sometimes in very critical areas, like byte code interpretation. Quote:
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I don't see my byte dup as a vector instruction, though. Quote:
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No difference between or.l #$1ff,d0 and or.w #$1ff,d0, ok ? Quote:
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01001110 00< ea > MOVE.L #i16,EA Quote:
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The only other way to fix it, is to reclaim line-A. Perhaps not the best thing to do either. Quote:
But really if i had this i wouldn't care if it's a long instruction or not. I needed it just too many times. Quote:
Would spare many long branches because RTS isn't necessarily nearby and quite a few RTS are here only because none were available in the routine. Ok, it's not targeted at speed ; rather, it's for code density. Even though it might help making code faster, i don't know. Quote:
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These instructions being true multiprecision shifts, you can do any size. Remember the discussion we had with Gunnar about the new instruction he needed for blitter emulation ? And i didn't write everything, i have more potential additions in store |
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04 August 2016, 22:14 | #15 | |
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The subject of disassembling Frontier happened to come up at work today (i love my job) and apparently the whole thing is PC relative despite being >600k in size, there are various jump tables in it.
But, generally, as frustrating as it is to have to LEA label(PC),An whenever i want to write to static storage, that's pretty rare for me, it's usually just for reading constants. d32(PC) would be really useful though. As for the more complex addressing modes of the 68020+, memory indirect and all that... how useful really are they? I can think of some uses, but mostly in conjunction with JSR/JMP to implement VTables of polymorphic classes. A version of Jmp that reads its effective address instead of jumping to it could be useful then. jsrm / jmpm d16(An) ; reads longword address pointed to by d16(An) and jumps to it i.e. same as the following: move.l d16(An),Am jsr / jmp (Am) Quote:
But the 68k branch encodings are another puzzle. Why is it even possible to branch to an odd address, if it cannot possibly be valid? Why didn't they simply use a 7-bit field instead of 8 and use the upper bit to indicate whether it is a short branch or a long one? Because then a long branch could be 24 bit, which is as big as the original 68k's address bus. Last edited by Mrs Beanbag; 04 August 2016 at 22:45. |
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05 August 2016, 00:21 | #16 | ||||
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bne .skip bsr function .skip: I could not find any statistics on whether conditional branches to subroutines were more likely to be taken or not. ARM has a conditional branch to subroutine with BLcc which could be analyzed but I couldn't find any statistics. If conditional branches are usually taken, then meynaf's macro works pretty well even without predication. If conditional branches to subroutines are usually not taken (which I suspect), then the macro is not efficient. A BSRcc could use static branch prediction appropriate for a branch to subroutine (much as DBcc uses different static prediction than Bcc on the 68060). There is an acceptable encoding available to add an extra word for the condition code of a BSRcc. However, a branch hint bit would allow for the most efficient (semi-)static branch prediction in all cases without increasing code size. I did find the following ARM code on the internet. Code:
CMP R1, R2 ; branch conditionally BLLT SUB_B ; if R1 < R2, then branch to SUB_B BLLE SUB_C ; if R1 =< R3, then branch to SUB_C BLGT SUB_D ; if R1 > R2, then branch to SUB_D BLGE SUB_F ; if R1 >= R2, then branch to SUB_F The case for RTScc is a little difference. The code that will be returned to is already likely in the ICache and it is acceptable to load the return code into the ICache if it is not as it will likely be returned to shortly anyway. I expect a branch over RTS could be problematic for predication also. I would like to see statistics of how common RTScc could be used and of whether the conditional return is more commonly taken or not. I expect a branch hint bit could be effective if predication could not be used but meynaf did come up with a 16 bit encoding which would be smaller than a Bcc+RTS. The case for it is not overly compelling but I believe it deserves more research. Quote:
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IMO, BITREV and BYTEREV are not so easy to understand. REVBITS.L and REVBYTES.L are easy to understandable but too long. BREV.L and REVB.L are shorter compromises. I would change them back if the majority prefers the original ColdFire names. I still have meynaf's post to get to. Yikes. |
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05 August 2016, 03:01 | #17 | |||||||||||||||||||
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They didn't show results unfortunately but it is easy to see a power savings for embedded. Fast processors should benefit also as the best dynamic branch prediction has several cycles latency before the prediction is ready. A cheaper and faster 2 bit saturating with (semi-)static prediction to improve it a little may be a better way to go while also being good for embedded. As for small results, the semi-static hint with profiling should be good for at least 10% improvement over static BTFN. The following article gives some results. http://www.ele.uri.edu/~uht/research...apers/bert.pdf Just a few percent difference in branch prediction accuracy makes a huge difference. Quote:
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You do like a complex instructions set . |
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05 August 2016, 09:40 | #18 | |||||||||||||
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Common cases are : Code:
; min/max stuff cmp.w (a1),d1 bhs.s .n0 move.w d1,(a1) .n0 cmp.w 2(a1),d2 bhs.s .n1 move.w d2,2(a1) .n1 cmp.w 4(a1),d3 bls.s .n2 move.w d3,4(a1) .n2 cmp.w 6(a1),d4 bls.s .n3 move.w d4,6(a1) .n3 Code:
; two messages depending on a condition lea msg1(pc),a0 tst something beq .done lea msg2(pc),a0 .done ; show msg here In second case it's not usable at all. This was just a quick look i've had in actual code, but nevertheless. Quote:
Being 1 OP means the encoding is small, but that's about all. And i'm certainly not for total crazy things such as SWAPA. Quote:
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Anyway for me a better name would have been SWW (swap words). Quote:
If compatibility weren't an issue i'd use Dn.B, Dn.W, Dn.L, An.L instead of Dn.W, Dn.L, An.W, An.L. Quote:
Indeed. Now consider and.l #$1ff,d0 vs bfextu d0{23:9},d0. Quote:
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Perhaps it could be a good idea to have a look in actual code to find some short immediate use cases. Quote:
That's still far simpler than x86. And we're CISC, after all |
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05 August 2016, 23:22 | #19 | ||||
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jmp ([d16,An]) jsr ([d16,An]) The 68020 address modes are good for OOP but OOP is bad for processor performance. Indirect branches are difficult for even modern processors to deal with. Quote:
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06 August 2016, 01:08 | #20 | ||||||||
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SWW.L would not be bad but REVW.L is more understandable, IMO. My preferred syntax is very clear at least. There may be too much use of REV with BREV.L, REVB.L and REVW.L though. Maybe REVB.L could be EREV.L or ESWAP.L for endian reverse or endian swap. I don't know. The originals aren't horrible either even if BYTEREV is a little long. Quote:
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The AND.L is simpler and what a compiler is most likely going to use. The AND.L #d16.w,Dn addressing mode is the same size as BFEXTU but it may be faster on some CPU implementations. Quote:
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I played with your mix and it is trickier than it first looks. It might have been a good algorithm for the programming competition. I came up with the following. Code:
mix: ; d0 = mask (trashed) ; d1 = number 1 (mixed result 1) ; d2 = number 2 (mixed result 2) ; d3 = scratch move.l d0,d3 ; pOEP and.l d1,d3 ; sOEP and.l d2,d0 ; pOEP eor.l d3,d2 ; sOEP eor.l d0,d1 ; pOEP eor.l d0,d2 ; sOEP eor.l d3,d1 ; pOEP I'm not a fan of the MIX EA,Rn:Rn using Rn:Rn which should be reserved for a high:low 64 bit value. I would just go for MIX EA,Rn,Rn. The ColdFire tried to limit instructions to 2 OPs also which is why it ended up with REM(S/U) EA,Dr:Dq when there is no 64 bit operation. It is confusing and didn't work for 64 bit REMS/REMU which is one of the reasons I created DIVUR/DIVSR. It also keeps me from using an alias of REMS->DIVSR and REMU->DIVSU like you suggested. Last edited by matthey; 08 August 2016 at 05:09. |
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