18 November 2022, 13:59 | #1 |
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Open source A500 simple SPI controller
I have been working on this idea for a very simple SPI controller for the Amiga 500 and I am pleased to announce that it is ready for release!
Called the "A500 simple SPI controller", this small internal device plugs into the 68K CPU socket and allows you to connect an internal SD card and an internal/external ENC28J60 ethernet controller to your Amiga 500. This SPI controller is designed to be as simple as possible so that anyone can build it, hence the "simple" SPI controller. The design uses no programmable logic chips but only jellybean 3.3V 74LVCXX logic chips and a jellybean quad analog switch. It also uses readily available cheap modules for the ethernet and SD-card interfaces. This design was done in Kicad 6.0 and all the files plus a lot more pictures can be found here: https://github.com/Mathesar/a500-simple-spi-hardware. Drivers are also provided and can be found here: https://github.com/Mathesar/a500-simple-spi-drivers The drivers are build upon the excellent previous work by Niklas Ekstrom and Mike Stirling. Hardware: Internal/external ethernet, I have to print some nice 3D enclosure for this... AmiTCP in action! Downloading some stuff from Aminet, pinging my favourite website... The SD card is more than 200% faster than a standard Amiga 500 floppy drive! |
18 November 2022, 18:13 | #2 |
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Very cool! It's always nice to see new open source Amiga hardware. Nicely done.
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18 November 2022, 19:19 | #3 |
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18 November 2022, 21:26 | #4 |
mä vaan
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Nice! Zorro version would be nice, but maybe too much to wish.
Though there are open source Zorro II passthrough for a Amiga 500 to use with sidecars. Which would mean more possible users? |
19 November 2022, 08:08 | #5 | |
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Quote:
It wouldn't be too hard too make a Zorro-II version but then I would probably use a CPLD or something similar. SPI interfaces are among the simplest interfaces to implement. The hard work is always in the software. A Zorro-II version could be a more sophisticated design with a hardware shifter and autoconfig logic contained within a small CPLD. That would easily be at least 10 times faster even on a 7MHz 68000. And the only thing that would have to change are the lowlevel SPI functions. Thinking about it.... an open source ethernet controller for big box Amiga's would be nice. I don't think any exist right? |
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19 November 2022, 17:26 | #6 | |
mä vaan
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Quote:
https://github.com/MHeinrichs/Zorro-LAN-IDE SPI could be lots of more than LAN, or mass storage. |
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19 November 2022, 22:04 | #7 |
Mighty Pirate
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Nice work, keep it up!
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19 November 2022, 22:35 | #8 |
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Nice! Well Done!
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20 November 2022, 05:06 | #9 |
Returning fan!
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Bravo!
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20 November 2022, 08:42 | #10 | |
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Quote:
Maybe the next project for me is to combine the 14MHz accelerator and the SPI controller in an nice external GVP HD8+ like design that plugs into the side expansion slot. Sort of like an ACA500+ but then good looking. I tried stacking the 14MHz accelerator stacks upon the simple SPI controller and that worked like a charm. Made everything go much faster but the low amount of fast ram (only 1MB) is a limiting factor so a new external design would need 4MB or more. What else would be interesting on SPI btw? An RTC clock? MP3 decoder? Last edited by Mathesar; 20 November 2022 at 08:48. |
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20 November 2022, 12:52 | #11 | ||
mä vaan
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Quote:
Quote:
I think that most import part would be make a standardized SPI control and library system with GUI, which would allow others make drivers for what they want. |
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20 November 2022, 13:29 | #12 |
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Absolutely, this is a key think for SPI, I2C and similar add-ons that are appearing. There are already some device driver libraries out there, it would make sense to keep things consistent and present a standard API so that one driver for e.g. an SD card reader can be used with any SPI interface by setting the appropriate options.
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20 November 2022, 15:08 | #13 | |
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Quote:
https://www.thingiverse.com/thing:4830638. That one looks a bit "boxy", but imagine it with a GVP HD8+ design but then a bit smaller... We don't need to house a whole 3.5" drive, just a (micro) SD card and some RAM chips.... |
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20 November 2022, 15:14 | #14 | |
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Quote:
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20 November 2022, 17:40 | #15 |
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Yep, I'm sure we have writing drivers and developing APIs is something I really need to get into. Every time I sit down to do something like that though I think "boring!" and instead cobble together a quick hardware-banging proof-of-concept and leave it at that :/
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20 November 2022, 18:45 | #16 | |
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Personally I think the overhead of a device may be too large. Just look at the SD or ENC28J60 driver code, lots of small consecutive read/write operations happening. I think the overhead of calling DoIo() or BeginIo() which then calls BeginIo(), message passing, task switching, etc would slow the system down too much. Or am I missing something and is the overhead manageable if we only do QUICKIO or something? I think a library or a library masquerading as a resource is way leaner. A library function can be called directly without any overhead. But a resource needs to be loaded by some application while a library is automatically loaded from disk by the OS.... So I would think it needs to be a library or maybe a device..... |
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20 November 2022, 23:50 | #17 |
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Mathesar: Nice I like to use this with your accelerator. Did you build any extra for sale?
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21 November 2022, 01:01 | #18 | |
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Let me know what you think about this proposal. The wiki is publicly editable if you want to edit there directly, or comment here and I can update later. |
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21 November 2022, 09:55 | #19 | |
ex. demoscener "Bigmama"
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Quote:
Won't this mean that it should support asynchronous transfer of larger buffers, which an exec device is perfect for (compared to a library) ? |
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21 November 2022, 10:16 | #20 |
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@Niklas:
Could the spi.device itself handle the aquire/relinguish when appropriate? It should be the one who knows if there is a separate spi bus for each unit, or if it is shared, right? |
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