ANDI.L #imm,Dn cycle count

[Bartman]

M68000 User's Guide (page 121) says 14 cycles, but WinUAE and https://www.atari-forum.com/viewtopic.php?t=16240 say 16 cycles.
I'm very much inclined to believe WinUAE and that Atari CPU-Tester are accurate, however that means that there may be more mistakes in Motorola's User's Manual.
There have probably already been discussions about Motorola's cycle tables but my google-fu eluded me this time.
Any thoughts?

[paraj]

.M68000UM is probably wrong with instruction timming for ANDI.L #<data>,Dn
instruction. It reads "14(3/0)" but, according to USP4325121, this
instruction is based on the same microwords than EORI.L #<data>,Dn and
ORI.L #<data>,Dn that have a "16(3/0)" timming. In addition, evaluation on
real hardware confirms the 16 cycles timing.

From ye olde Yacht

[Jobbo]

I always use EASy68k for checking cycle times and that is reporting 16 cycles.

[Bartman]

Originally Posted by paraj

From ye olde Yacht

Thanks!
However, that brings me to my next "exception". CMPI.L #imm, Dn also being shown as 14 in M68000UM and Yacht, but as 16 in the Atari CPU-Tester.

[Don_Adan]

I will say 14 cycles is best case, 16 cycles is for other cases.

[paraj]

Originally Posted by Bartman

Thanks!
However, that brings me to my next "exception". CMPI.L #imm, Dn also being shown as 14 in M68000UM and Yacht, but as 16 in the Atari CPU-Tester.

Pretty sure 14 is right, and WinUAE seems to agree. Do you have a link to the Atari CPU-tester?


If you have suitable machine hooked up you can use Toni's cputester to verify the results as it has a timing test mode (but in all likelihood this was already done).

[deimos]

Originally Posted by Don_Adan

I will say 14 cycles is best case, 16 cycles is for other cases.

Is there any way that an AND like that would not be a constant number of cycles though?

[hooverphonique]

Originally Posted by deimos

Is there any way that an AND like that would not be a constant number of cycles though?

The AND instruction is constant, the CMP could be variable depending on the result of the comparison

[npomarede]

Originally Posted by Bartman

M68000 User's Guide (page 121) says 14 cycles, but WinUAE and https://www.atari-forum.com/viewtopic.php?t=16240 say 16 cycles.
I'm very much inclined to believe WinUAE and that Atari CPU-Tester are accurate, however that means that there may be more mistakes in Motorola's User's Manual.
There have probably already been discussions about Motorola's cycle tables but my google-fu eluded me this time.
Any thoughts?

Hi, Hatari dev here

wow, this is such an old thread from 2009 in atari-forum ...
Don't trust fully Atari cycles counting when coding on Amiga, because on Atari all cycles are rounded to the next 4 cycles.
So it's certainly 14 cycles as reported by motorola doc and winuae, which is rounded to 16 cycles under Atari, but that's specific to how Atari allocate memory access between cpu and video.


Nicolas

[Toni Wilen]

Only 68000 instructions (if I didn't miss anything) that have variable cycle usage are:

- register shift instructions
- mul/div
- bset/bclr/bchg #/dn,dn that add 2 extra cycles if source bit number is >= 16.
- bcc (branch taken/not taken difference)
- dbcc (branch taken/not taken/counter expired difference)
- stop

[a/b]

Page 121 (this is what I pressume you're referring to):

Instruction	Size		op #,Dn		op #,An		op #,M
ANDI		Byte, Word	8(2/0)		—		12(2/1)+
		Long		14(3/0)		—		20(3/2)+

But also on page 120 (table 8-4), for ADD/AND/OR/SUB with Long and op <ea>,Dn:
6(1/0)+**
+ Add effective address calculation time.
** The base time of six clock periods is increased to eight if the effective address mode is register direct or immediate (effective address time should also be added).

Which should then translate to 8+8=16 (and not 6+8) for those instructions, but on page 121 (table 8-5) some are listed as 14 (ANDI) and some as 16 (ADDI, ORI, SUBI). For ADD and SUB I'd understand why (carry over between words), but AND and OR being listed as different is weird.