Chips for AGA reproduction

[PurpleMelbourne]

AGA chips costs about 150 euros for a full new set, and the price rising like BitCoin.

So we need to reproduce the old chips in modern PAL, GAL, CPLD and FPGA Programmable Logic chips. But only larger CPLD's and FPGA's are big enough.

MiniMig and MISTer are the most well known efforts.
These bundle the entire system into a single Programmable Logic chip. They have spearheaded great work which can now branch out to the real Amiga's.

Separate reproductions of each chip is needed. Once we have great reproductions, we can work on making superior performance replacements.

Dave Haynie answered my question on this topic that 5V tolerant LVCMOS (low voltage complimentary programmable logic devices) CPLD's are best used for electrical compatibility with the 5V TTL (transistor to transistor logic) design of the Amiga.

Support chips like Gary, Gayle and Bridgette can therefore be made in currently manufactured chips like the Xilinx XC9500 family of CPLD chips.

Agnus, Alice, Denise and Lisa are much bigger and will require FPGA chips to fit that much logic.
Akiko and Budgie also require internal memory called BRAM (Block RAM) which is only found in more advanced of the old FPGA's.

PROBLEM

The Amiga is a 5 volt computer, and modern Programmable Logic chips start at 3.3 volts and go down from there. This is a problem for us as it means we can't use the new chips without adding lots of extra circuitry to change voltage.

SOLUTION

NOS (New Old Stock) of the formerly expensive high end chips are useful to us while we work through our development stage where we need to remain 5 volt compatible.
Once we have new 3.3 volt Amiga's, we can move to newer chips.

Here are the chips I found with 30,000 gates or more.

LATTICE

ispXPGA

1. LFX125B
2. LFX125C
3. LFX125EB
4. LFX125EC
5. LFX200B
6. LFX200C
7. LFX200EB
8. LFX200EC
9. LFX500B
10. LFX500C
11. LFX500EB
12. LFX500EC
13. LFX1200B
14. LFX1200C
15. LFX1200EB
16. LFX1200EC

XILINX

XC4000 (5V chips)

1. XC4036
2. XC4044
3. XC4052
4. XC4062
5. XC4085

Spartan (5V) and Spartan XL (3.3V chips but 5V tolerant)

1. XCS30 and XC2S30XL
2. XCS40 and XC2S40XL

Spartan 2 (3.3V but 5V tolerant LVCMOS, LVTTL and PCI_5V modes)

1. XC2S30
2. XC2S50
3. XC2S100
4. XC2S150
5. XC2S200

Spartan 2E (3.3V but 5V tolerance with external resistors)

1. XC2S50E
2. XC2S100E
3. XC2S150E
4. XC2S200E
5. XC2S300E
6. XC2S400E
7. XC2S600E

[PurpleMelbourne]

place holder

[AJCopland]

As an aside to using 5V compatible FPGAs/CPLDs TF was going to use level shifters on a daughter board for the ReAgnus

https://www.exxoshost.co.uk/forum/vi...hp?f=65&t=2828

[jasonsbeer]

Originally Posted by AJCopland

As an aside to using 5V compatible FPGAs/CPLDs TF was going to use level shifters on a daughter board for the ReAgnus

https://www.exxoshost.co.uk/forum/vi...hp?f=65&t=2828

Yup.

To maximize length of time before CPLD/FPGA end of life, 5V should not be used. Logic level shifters are probably the way to go. With the size of SMD components, you can put a lot of them on a small PCB intended as an IC replacement.

[pandy71]

Some logic like 74LVC is more than OK - side to this FPGA with lower I/O can be used if some latch/multiplexing will be used (Amiga chipset bus is quite slow - less than 8Mhz most signals except video lines where max is 28MHz).
Nowadays seem there is interesting alternative to FPGA - TI ARM (but other vendor may offer similar solutions - for example XMOS solutions) https://training.ti.com/pru-training-series - dedicated I/O coprocessors able to handle up 200MHz software I/O - perfect as base for experiments (software driven HW).

[PurpleMelbourne]

Originally Posted by pandy71

Some logic like 74LVC is more than OK.

The trouble comes when you want to do things like make an entire board to fit inside the 30mm x 30mm Agnus socket.

Space becomes a premium and adding four extra voltage changing chips is four chips too many.

I've got a double decker Agnus replacement, but it seems no one is interested because its too big. It uses a 3.3volt FPGA and voltage changing chips exactly as you recommend. But that is the problem I'm trying to solve.

[pandy71]

Originally Posted by PurpleMelbourne

The trouble comes when you want to do things like make an entire board to fit inside the 30mm x 30mm Agnus socket.

Space becomes a premium and adding four extra voltage changing chips is four chips too many.

I've got a double decker Agnus replacement, but it seems no one is interested because its too big. It uses a 3.3volt FPGA and voltage changing chips exactly as you recommend. But that is the problem I'm trying to solve.

But this is common problem for retrocomputing and only one solution is to use 5V native logic - possible but at a horrendous price - still there is lot of old, 5V logic on market - mostly military and space grade... some companies like Rochester Electronics bought all available silicon dies directly from manufacturers and de facto created monopoly on market...
So or level conversion or enormous cost...

[Locutus]

If you are going to rebuild the whole chipset why do you need to stick to 5V? What is it at that point you still need to interface with? The CPU itself, so that only leaves you 1 critical point of low voltage to 5V shifting....

Aaand then the question rises, what is this trying to solve that the various FPGA re-implementations already do?

[Daedalus]

Presumably it's intended as 1:1 drop-in replacements for custom chips on existing motherboards, which have lots of other 5V logic on their buses besides the custom chips. Dropping the bus to 3.3V or lower isn't a problem if you're designing an entirely new machine, but then you're getting into FPGAArcade and MiSTer territory as you point out, so the point is diminished.

[kriz]

Would be great with new chips for new motherboard remakes

[AJCopland]

Originally Posted by PurpleMelbourne

The trouble comes when you want to do things like make an entire board to fit inside the 30mm x 30mm Agnus socket.

Space becomes a premium and adding four extra voltage changing chips is four chips too many.

I've got a double decker Agnus replacement, but it seems no one is interested because its too big. It uses a 3.3volt FPGA and voltage changing chips exactly as you recommend. But that is the problem I'm trying to solve.

Ah I understand new, my apologies. Still I think that sometimes the TF approach taken with ReAgnus looks promising. The footprint was pretty small.

[PurpleMelbourne]

3.3volt supply chips only need a voltage chip if the io signals are 5volt compatible. They don't need much extra room for that one voltage chip.

The list at the top has both fully 5volt chips, and also 3.3volt chips with 5volt io signal pins.

I hope this list is useful.
If anyone else has extra chips to be listed, I'll edit them into the first post

[pandy71]

Quick search at Mouser for 5V compliant programmable devices:

https://eu.mouser.com/Semiconductors...yvm6j0Z1yvm6ir
https://eu.mouser.com/Semiconductors...yvm6bqZ1yo72rt
https://eu.mouser.com/Semiconductors...6bqZ1yo5p7fSGT

Quick Logic offer also 5V compliant devices (pASIC3 and QuickRam) https://forum.quicklogic.com/viewtopic.php?p=521

It may be sane approach to separate 5V tolerant I/O from main (large FPGA but with relatively lo I/O count) by programming 5V tolerant device with some serializer/deserializer (serdes) functionality so main FPGA can be hooked with relatively low number of I/O signals (FPGA cost depends highly on the number of the available I/O's).

[b0lt-thrower]

I'm going to be watching this development with great interest. Would be amazing to build up one of those A4000 boards that has PCI slots and the works, you know?

[Mick]

Maybe start with something easier like A600? if someone could program like-for-like chips I'm sure it wouldn't be too hard to modify the board I did in Kicad to take the new footprints/pinouts?

It'd be better to go with new available chips though rather than old stock? like the one's pandy71 has suggested?

Having the entire custom chipset operating within a single FPGA just seems a bit too "software" to me. I'd prefer 1:1 replica chips (nothing more/nothing less) even if they are physically different (maybe look to improve them later).

Who is going to replicate the chips in software though? surely that's the hard part?

[Stedy]

Originally Posted by Mick

Maybe start with something easier like A600? if someone could program like-for-like chips I'm sure it wouldn't be too hard to modify the board I did in Kicad to take the new footprints/pinouts?

It'd be better to go with new available chips though rather than old stock? like the one's pandy71 has suggested?

Having the entire custom chipset operating within a single FPGA just seems a bit too "software" to me. I'd prefer 1:1 replica chips (nothing more/nothing less) even if they are physically different (maybe look to improve them later).

Who is going to replicate the chips in software though? surely that's the hard part?

Top Man Mick, you asked the hard question.

Consider the A600, you'd need to replicate Agnus, Denise, Gayle, Paula and the VIAs/CIAs. A ballpark number for the hours per device, for a proof of concept, prototype design would be 500-1000 hours per device. For 5 devices, that's 2500-5000 hours, I work 1662 hours a year!

You could simplify it, if you change the design a little. If you make all custom chips 3.3V and keep the CPU + ROM as 5V parts, it becomes a bit easier. On the A5600, the existing U21/U22 CPU/custom chip access device would translate 5V to 3.3V. You would need 2x16 bit buffers to convert address bus + control signals to +3.3V logic.

You'd then need to swap the chip RAM to 3.3V or buffer it. The easy route would be to replace it with 3.3V SRAM as DRAM was not widely available in 3.3V (if at all).

You'd need a 5V tolerant CPLD for the CIA/VIAs to handle the 5V floppy interface, mouse/joystick and the printer port. The serial interface could drop to 3.3V and use modern RS232 line drivers.

The more buffers you add, the more you need to add onto the tracking. Mick will remember this well.

The biggest risk to the design is the new FPGA/CPLD being too fast and drawing bigger gulps of power. In my previous job, I designed new CPUs/FPGAs into legacy systems, some were 20+ years old. The edge rates and power requirements can easily trip you up. We did create some tiled FPGA ASIC replacements. For us, if they cost £500-£1000 each it was cheaper than the cost of replacing the main processor + FPGA which cost an 8 figure sum!

Originally Posted by pandy71

Quick search at Mouser for 5V compliant programmable devices:

https://eu.mouser.com/Semiconductors...yvm6j0Z1yvm6ir
https://eu.mouser.com/Semiconductors...yvm6bqZ1yo72rt
https://eu.mouser.com/Semiconductors...6bqZ1yo5p7fSGT

Quick Logic offer also 5V compliant devices (pASIC3 and QuickRam) https://forum.quicklogic.com/viewtopic.php?p=521

They are very long in the tooth. The Microchip/Atmel parts are surprisingly still made. Quicklogic are only making FPGAs/CPLD as the US Government asked them to keep making them for critical projects.

The longest lifetimes are the Xilinx XC95XX and Lattice ispMach4000, both have <5 years left.

I'm not trying to discourage you, rather make you think about the commitment a project like this would entail.

[pandy71]

Originally Posted by Stedy

They are very long in the tooth. The Microchip/Atmel parts are surprisingly still made. Quicklogic are only making FPGAs/CPLD as the US Government asked them to keep making them for critical projects.

The longest lifetimes are the Xilinx XC95XX and Lattice ispMach4000, both have <5 years left.

I'm not trying to discourage you, rather make you think about the commitment a project like this would entail.

This in not about discourage me or someone else - this is about choices and each engineer is aware of such choices (i hope) - i agree with you - there is something else to create replacement part for old HW and something else to create new Amiga where everything can be done in modern HW (so LV and everything fit inside single FPGA).

And as i wrote earlier - 5V parts will be available on market but with prices only going higher so now is orange light (not green as this could be valid for 10 years ago) to start collecting parts in advance for ongoing years.
Perhaps some alternative approach can be like use of some glue logic like Dialog Semiconductor GreenPAK series for example SLG46533.
Anyway voltage translators seem to be long term solution... or... decapping real chips and order ASIC's in 5V compliant technology...

[Bruce Abbott]

Originally Posted by Stedy

The Microchip/Atmel parts are surprisingly still made.

And I have a few that need to be used, so...

I'm not trying to discourage you, rather make you think about the commitment a project like this would entail.

Right now the easiest way to secure Amiga custom chips is to just buy an old Amiga, so if that is all you want then there is no urgency to develop replacements. But eventually the supply will dry up, so it wouldn't hurt to start planning for replacements now.

It also opens up the possibility of developing enhanced chips that could be 'drop-in' replacements - just like Commodore did with the original Angus and Denise. Things like:-

- Enhanced Blitter
- Chunky graphics
- 'Text' mode (tiled graphics)
- other modes suitable for emulating older computers
- More chip RAM
- True 12, 14 or 16 bit sound
- More sound channels
- Panning
- High speed Buffered serial port
- High speed Parallel port (CIA replacement)

Imagine if anyone with an A500 etc. could pop one of these enhanced chips into their machine to make it compatible with new software that needs it. We could finally get the improvements everyone wanted 'back in the day', but Commodore was too slack to provide them!

We don't have to do it all at once, nor do we necessarily have to achieve a high level of compatibility. But it does need to be widely accepted and available for the enhancements to be worthwhile.

Years ago I developed a floppy drive interface for the CD32 because I desperately needed it but couldn't afford an SX-32 and didn't want to cannibalize another Amiga for CIA chips. The result - made from standard TTL logic - implemented just enough of the CIA chips to get the floppy drive working with the OS. It didn't work with some games that hit the hardware directly, but that didn't matter to me - I had what I wanted (which wasn't to play games that probably wouldn't run on a CD32 anyway). If I had a CD32 today I would develop a more sophisticated version with a CPLD.

[Chucky]

I do not understand those who want well extra features in the chipset..
it would ONLY add incompability like we had when we got AGA etc.

and as that would require reprogramming software anyway why not "just" do it as an extra hardware? like RTG etc..

I just do not get it why it would be as a "chipset thing"

[pandy71]

Originally Posted by Chucky

I do not understand those who want well extra features in the chipset..
it would ONLY add incompability like we had when we got AGA etc.

and as that would require reprogramming software anyway why not "just" do it as an extra hardware? like RTG etc..

I just do not get it why it would be as a "chipset thing"

Very simple to explain - this is something we (Amiga users) expected to be done by Commodore and Commodore failed on many ways to do so.

Some of those features could be present since Amiga was born, some of those features added to ECS, AGA and expected later another versions of the chipset.

Having some standard and functionality present in every Amiga is a mandatory condition to make those features supported by software - especially now when so many new things is created for Amiga (thanks to technology progress) we need to have some uniformity, some standards to avoid Linux situation where you have many competing standards and wasted resources. So for example any new Amiga CPU should be compatible with Vampire ISA so software can be reused.

And incompatibility can be workarounded on many ways - at first it can be avoided by providing new functionality in parallel to already existing.
At some point Commodore should focus on using general I/O bus (PCI/PCIex) and for example provide backward compatibility by inserting video/audio as overlay to any GPU so it could be 100% HW/SW legacy compatible and at the same time open and capable to grow in future.
Technically feeding 60 - 80MBps over bus (even on PCI many years ago) could be easily done if done HW wisely.